| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10300/ |
| am33_5.s | 14 asr 0x7ffefdfc,r2
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/xgate/ |
| all_insns.s | 18 L14: asr r0, #3
19 L15: asr r1, r2
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 29 asr, enumerator in enum:llvm::ARM_AM::ShiftOpc
48 case ARM_AM::asr: return "asr";
59 case ARM_AM::asr: return 2;
105 // reg [asr|lsl|lsr|ror|rrx] reg
106 // reg [asr|lsl|lsr|ror|rrx] imm
|
| /external/llvm/test/MC/AArch64/ |
| arm64-aliases.s | 46 tst x2, x20, asr #0
55 ; CHECK: tst x2, x20, asr #0 ; encoding: [0x5f,0x00,0x94,0xea]
64 cmn w8, w9, asr #3
73 ; CHECK: cmn w8, w9, asr #3 ; encoding: [0x1f,0x0d,0x89,0x2b]
86 cmp w8, w9, asr #3
99 ; CHECK: cmp w8, w9, asr #3 ; encoding: [0x1f,0x0d,0x89,0x6b]
119 neg x0, x1, asr #1
120 ; CHECK: neg x0, x1, asr #1
127 negs x0, x1, asr #1
128 ; CHECK: negs x0, x1, asr #
[all...] |
| arm64-arithmetic-encoding.s | 111 add x12, x13, x14, asr #39
118 ; CHECK: add x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x8b]
125 sub x12, x13, x14, asr #39
132 ; CHECK: sub x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xcb]
139 adds x12, x13, x14, asr #39
146 ; CHECK: adds x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xab]
153 subs x12, x13, x14, asr #39
160 ; CHECK: subs x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xeb]
396 asr w1, w2, w3
397 asr x1, x2, x
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| thumb2_bad_reg.s | 60 @ ASR (immediate)
61 asr r13, r0, #1
62 asr r15, r0, #1
63 asr r0, r13, #1
64 asr r0, r15, #1
65 @ ASR (register)
66 asr.w r13, r0, r1
67 asr.w r15, r0, r1
68 asr.w r0, r13, r1
69 asr.w r0, r15, r
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68hc11/ |
| all_insns.s | 48 L44: asr 163,X
49 L45: asr symbol90
50 L46: asr 37,X
|
| /art/runtime/interpreter/mterp/arm/ |
| header.S | 137 asr \tmp, #1
|
| /external/freetype/include/freetype/internal/ |
| ftcalc.h | 56 mov a, t, asr #31 /* a = (hi >> 31) */
88 "mov %0, %2, asr #31\n\t" /* %0 = (hi >> 31) */
|
| /external/libavc/common/arm/ |
| ih264_iquant_itrans_recon_dc_a9.s | 137 asr r6, r6, #4 @q0 = (pi2_src[0]*pu2_iscal_mat[0]*pu2_weigh_mat[0] + rnd_fact)<<(u4_qp_div_6-4)
144 asr r6, r6, #6 @i_macro >>6 = DC output of 2-stage transform
256 asr r6, r6, #6 @q0 = (pi2_src[0]*pu2_iscal_mat[0]*pu2_weigh_mat[0] + rnd_fact)<<(u4_qp_div_6-4)
258 asr r6, r6, #6 @i_macro >>6 = DC output of 2-stage transform
|
| /external/libgdx/extensions/gdx-freetype/jni/freetype-2.6.2/include/freetype/internal/ |
| ftcalc.h | 56 mov a, t, asr #31 /* a = (hi >> 31) */
88 "mov %0, %2, asr #31\n\t" /* %0 = (hi >> 31) */
|
| /external/pdfium/third_party/freetype/include/freetype/internal/ |
| ftcalc.h | 56 mov a, t, asr #31 /* a = (hi >> 31) */
88 "mov %0, %2, asr #31\n\t" /* %0 = (hi >> 31) */
|
| /external/webrtc/webrtc/common_audio/signal_processing/ |
| complex_bit_reverse_arm.S | 45 asr r2, #1 @ l >>= 1;
|
| /frameworks/av/media/libstagefright/codecs/mp3dec/src/ |
| pv_mp3dec_fxd_op_arm.h | 190 eor a, b, b, asr #31
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/epiphany/ |
| sample.s | 47 test3i asr
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mcore/ |
| allinsn.s | 18 test asr "r11, R12" // Uppercase R is allowed as a register prefix
|
| /external/libhevc/common/arm64/ |
| ihevc_deblk_chroma_vert.s | 86 adds x3,x7,x2,asr #1
106 adds x2,x6,x2,asr #1
|
| /frameworks/av/media/libstagefright/codecs/aacenc/src/asm/ARMV7/ |
| PrePostMDCT_v7.s | 37 movs r1, r1, asr #2
99 movs r1, r1, asr #2
|
| Radix4FFT_v7.s | 34 mov r1, r1, asr #2
140 movs r1, r1, asr #2
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/xstormy16/ |
| allinsn.d | 850 6a6: 00 36 asr r0,r0
851 6a8: ff 36 asr r15,r15
852 6aa: 88 36 asr r8,r8
853 6ac: 77 36 asr r7,r7
854 6ae: 11 36 asr r1,r1
855 6b0: a5 36 asr r5,r10
856 6b2: 53 36 asr r3,r5
857 6b4: b6 36 asr r6,r11
860 6b6: 00 37 asr r0,#0x0
861 6b8: ff 37 asr r15,#0x
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/ |
| cris.exp | 431 test_template_insn_reg regreg asr.b 78 "" "" 44
432 test_template_insn_reg regreg asr.w 79 "" "" 44
433 test_template_insn_reg regreg asr.d 7a "" "" 44
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
| vector2.s | 22 //Dreg = VIT_MAX ( Dreg , Dreg ) (ASR) ; /* shift history bits right (b) */
25 //Dreg_lo = VIT_MAX ( Dreg ) (ASR) ; /* shift history bits right (b) */
27 r7 = vit_max (r1, r0) (asr) ; /* shift right, dual operation */
30 r3 = vit_max (r4, r5) (asr) ; /* shift right, dual operation */
32 r1 = vit_max (r2, r3) (asr) ; /* shift right, dual operation */
34 r7 = vit_max (r0, r1) (asr) ; /* shift right, dual operation */
36 r5 = vit_max (r6, r7) (asr) ; /* shift right, dual operation */
40 r3.l = vit_max (r1)(asr) ; /* shift right, single operation */
43 r2.l = vit_max (r3)(asr) ; /* shift right, single operation */
45 r6.l = vit_max (r7)(asr) ; /* shift right, single operation *
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb2-instructions.s | 51 adcs.w r0, r1, r3, asr #32
60 @ CHECK: adcs.w r0, r1, r3, asr #32 @ encoding: [0x51,0xeb,0x23,0x00]
119 add r5, r9, r2, asr #32
140 @ CHECK: add.w r5, r9, r2, asr #32 @ encoding: [0x09,0xeb,0x22,0x05]
246 and r1, r4, r8, asr #3
252 @ CHECK: and.w r1, r4, r8, asr #3 @ encoding: [0x04,0xea,0xe8,0x01]
258 @ ASR (immediate)
260 asr r2, r3, #12
263 asr r2, r3, #4
266 asr r3, #1
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_intra_pred_filters_luma_mode_19_to_25.s | 149 asr r9, r9, #5
560 mov lr,r5,asr #5 @if(fract_prev > fract)
576 mov lr,r5,asr #5 @ pos >> 5
597 mov lr,r5,asr #5 @if(fract_prev > fract)
619 mov lr,r5,asr #5 @if(fract_prev > fract)
|
| ihevc_weighted_pred_bi_default.s | 141 @asr r6,#1
212 asr r9,r6,#1
253 asr r9,r6,#1
306 asr r9,r6,#1
355 asr r9,r6,#1
|
