| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 220 case MVT::f32:
|
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 232 if (LS->getMemoryVT() == MVT::f32 && Subtarget->hasMips4_32r2())
|
| MipsSEISelLowering.cpp | 103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
180 setOperationAction(ISD::SELECT, MVT::f32, Legal);
181 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
191 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
192 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
193 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
194 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| unwind-ok.s | 100 .spillreg.p p63, f16, f32
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 260 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
267 while (SVT != MVT::f32 && SVT != MVT::f16) {
684 if (CFP->getValueType(0) == MVT::f32 &&
[all...] |
| LegalizeFloatTypes.cpp | 13 // "soft float". For example, turning f32 arithmetic into operations using i32.
37 VT == MVT::f32 ? Call_F32 :
439 // There's only a libcall for f16 -> f32, so proceed in two stages. Also, it's
440 // entirely possible for both f16 and f32 to be legal, so use the fully
442 if (Op.getValueType() == MVT::f16 && N->getValueType(0) != MVT::f32) {
443 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op);
444 if (getTypeAction(MVT::f32) == TargetLowering::TypeSoftenFloat)
467 EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32);
471 if (N->getValueType(0) == MVT::f32)
475 RTLIB::Libcall LC = RTLIB::getFPEXT(MVT::f32, N->getValueType(0))
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 82 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
121 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
125 setOperationAction(ISD::SELECT, MVT::f32, Custom);
129 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
138 setOperationAction(ISD::FREM, MVT::f32, Expand);
185 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
265 setOperationAction(ISD::FSIN, MVT::f32, Expand);
267 setOperationAction(ISD::FCOS, MVT::f32, Expand);
269 setOperationAction(ISD::FPOW, MVT::f32, Expand)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | [all...] |
| /external/v8/test/mjsunit/es6/ |
| destructuring.js | 964 // function f32({x = eval("a")}, ...a) { 'use strict'; return x[0] }
965 // assertThrows(() => f32({}), ReferenceError);
966 // assertEquals(4, f32({a: [4]}, 5));
|
| /external/clang/test/CodeGen/ |
| arm64-arguments.c | 125 void f32(struct s32 s) { } function
126 // CHECK: @f32([1 x double] %{{.*}})
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_print.cpp | 192 "f16", "f32", "f64",
383 case TYPE_F32: PRINT("%f", reg.data.f32); break;
|
| /external/mesa3d/src/gallium/state_trackers/d3d1x/d3d1xshader/src/ |
| sm4_parse.cpp | 305 dcl.f32 = read32();
|
| /external/skia/src/views/ |
| SkEvent.cpp | 16 f32 = 0;
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
168 // f32/f64 are legal, f80 is custom.
191 // f32 and f64 cases are Legal, f80 case is not
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
215 // f32 and f64 cases are Legal, f80 case is not
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand)
[all...] |
| /external/valgrind/memcheck/tests/ |
| deep-backtrace.c | 32 int f32(int *p) { return f31(p); } function
33 int f33(int *p) { return f32(p); }
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 141 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
145 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
152 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
210 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
212 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
221 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
223 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
237 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 96 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
99 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
342 // since <2 x f32> isn't a legal type.
406 // We have fused multiply-addition for f32 and f64 but not f128.
407 setOperationAction(ISD::FMA, MVT::f32, Legal);
418 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
419 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
426 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
472 case MVT::f32:
707 if (VT == MVT::f32)
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 65 case MVT::f32: return "MVT::f32";
|
| /external/v8/test/cctest/ |
| test-asm-validator.cc | 393 "var f32 = new stdlib.Float32Array(buffer); " \
492 CHECK_VAR_NEW_SHORTCUT(f32, Bounds(cache.kFloat32Array));
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips16-intermix.s | 1707 .globl f32
1709 .ent f32
1710 f32: label
1876 .end f32
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/ |
| mips16-intermix-2.s | 1707 .globl f32
1709 .ent f32
1710 f32: label
1876 .end f32
[all...] |
| /external/llvm/test/MC/ARM/ |
| neon-mov-encoding.s | 149 vmvn.f32 d1, d2
|
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | 35 Float f32[4]; member in union:_V128
70 if (isnormal(v->f32[0]) && isnormal(v->f32[1]) && isnormal(v->f32[2])
71 && isnormal(v->f32[3]) && isnormal(v->f64[0]) && isnormal(v->f64[1]))
218 block[i].f32[0] = randFloat();
219 block[i].f32[1] = randFloat();
220 block[i].f32[2] = randFloat();
221 block[i].f32[3] = randFloat();
[all...] |
| /external/skia/src/core/ |
| SkPaint.cpp | 1802 uint32_t f32; member in union:Scalar32
[all...] |
