| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| armv8-a+fp.s | 7 vseleq.f32 s0, s0, s0
8 vselvs.f32 s1, s1, s1
9 vselge.f32 s30, s30, s30
10 vselgt.f32 s31, s31, s31
15 vmaxnm.f32 s0, s0, s0
16 vmaxnm.f32 s1, s1, s1
17 vmaxnm.f32 s30, s30, s30
18 vmaxnm.f32 s31, s31, s31
23 vminnm.f32 s0, s0, s0
24 vminnm.f32 s1, s1, s
[all...] |
| neon-cond-bad.l | 6 [^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2'
7 [^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 q0,q1,q2'
8 [^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2'
9 [^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 q0,q1,q2'
10 [^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2'
11 [^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 q0,q1,q2'
12 [^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2'
13 [^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 q0,q1,q2'
14 [^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2'
15 [^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 q0,q1,q2
[all...] |
| vfp1xD.d | 11 0+004 <[^>]*> eeb40ac0 (vcmpe\.f32|fcmpes) s0, s0
12 0+008 <[^>]*> eeb50ac0 (vcmpe\.f32 s0, #0.0|fcmpezs s0)
13 0+00c <[^>]*> eeb40a40 (vcmp\.f32|fcmps) s0, s0
14 0+010 <[^>]*> eeb50a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
15 0+014 <[^>]*> eeb00ac0 (vabs\.f32|fabss) s0, s0
16 0+018 <[^>]*> eeb00a40 (vmov\.f32|fcpys) s0, s0
17 0+01c <[^>]*> eeb10a40 (vneg\.f32|fnegs) s0, s0
18 0+020 <[^>]*> eeb10ac0 (vsqrt\.f32|fsqrts) s0, s0
19 0+024 <[^>]*> ee300a00 (vadd\.f32|fadds) s0, s0, s0
20 0+028 <[^>]*> ee800a00 (vdiv\.f32|fdivs) s0, s0, s
[all...] |
| neon-suffix-bad.s | 3 add.f32 r0, r0, r0
4 faddd.f32 d0, d0, d0
9 add.f32 r0, r0, r0
10 faddd.f32 d0, d0, d0
|
| vfma1.d | 13 00000000 <[^>]*> ee000a00 vmla.f32 s0, s0, s0
15 00000008 <[^>]*> f2000d10 vmla.f32 d0, d0, d0
16 0000000c <[^>]*> f2000d50 vmla.f32 q0, q0, q0
17 00000010 <[^>]*> eea00a00 vfma.f32 s0, s0, s0
19 00000018 <[^>]*> f2000c10 vfma.f32 d0, d0, d0
20 0000001c <[^>]*> f2000c50 vfma.f32 q0, q0, q0
21 00000020 <[^>]*> ee000a40 vmls.f32 s0, s0, s0
23 00000028 <[^>]*> f2200d10 vmls.f32 d0, d0, d0
24 0000002c <[^>]*> f2200d50 vmls.f32 q0, q0, q0
25 00000030 <[^>]*> eea00a40 vfms.f32 s0, s0, s
[all...] |
| neon-cond-bad-inc.s | 21 .macro dyadic_eq op eq="eq" f32=".f32"
23 \op\eq\f32 d0,d1,d2
24 \op\eq\f32 q0,q1,q2
33 .macro monadic_eq op eq="eq" f32=".f32"
35 \op\eq\f32 d0,d1
36 \op\eq\f32 q0,q1
48 cvt s32 f32
49 cvt u32 f32
[all...] |
| half-prec-neon.d | 8 0+0 <[^>]*> f3b60602 vcvt\.f16\.f32 d0, q1
9 0+4 <[^>]*> f3b6a706 vcvt\.f32\.f16 q5, d6
|
| neon-fma-cov.s | 11 regs3_1 vfma vfma .f32
12 regs3_1 vfms vfms .f32
|
| vfp-fma-arm.d | 8 0[0-9a-f]+ <[^>]+> eea00a81 vfma\.f32 s0, s1, s2
10 0[0-9a-f]+ <[^>]+> 0ea00a81 vfmaeq\.f32 s0, s1, s2
12 0[0-9a-f]+ <[^>]+> eea00ac1 vfms\.f32 s0, s1, s2
14 0[0-9a-f]+ <[^>]+> 0ea00ac1 vfmseq\.f32 s0, s1, s2
16 0[0-9a-f]+ <[^>]+> ee900ac1 vfnma\.f32 s0, s1, s2
18 0[0-9a-f]+ <[^>]+> 0e900ac1 vfnmaeq\.f32 s0, s1, s2
20 0[0-9a-f]+ <[^>]+> ee900a81 vfnms\.f32 s0, s1, s2
22 0[0-9a-f]+ <[^>]+> 0e900a81 vfnmseq\.f32 s0, s1, s2
|
| neon-cond-bad_t2.d | 19 0[0-9a-f]+ <[^>]+> ff01 0d12 vmuleq\.f32 d0, d1, d2
20 0[0-9a-f]+ <[^>]+> ff02 0d54 vmuleq\.f32 q0, q1, q2
22 0[0-9a-f]+ <[^>]+> ef01 0d12 vmlaeq\.f32 d0, d1, d2
23 0[0-9a-f]+ <[^>]+> ef02 0d54 vmlaeq\.f32 q0, q1, q2
25 0[0-9a-f]+ <[^>]+> ef21 0d12 vmlseq\.f32 d0, d1, d2
26 0[0-9a-f]+ <[^>]+> ef22 0d54 vmlseq\.f32 q0, q1, q2
28 0[0-9a-f]+ <[^>]+> ef01 0d02 vaddeq\.f32 d0, d1, d2
29 0[0-9a-f]+ <[^>]+> ef02 0d44 vaddeq\.f32 q0, q1, q2
31 0[0-9a-f]+ <[^>]+> ef21 0d02 vsubeq\.f32 d0, d1, d2
32 0[0-9a-f]+ <[^>]+> ef22 0d44 vsubeq\.f32 q0, q1, q
[all...] |
| armv8-a+fp.d | 8 0[0-9a-f]+ <[^>]+> fe000a00 vseleq.f32 s0, s0, s0
9 0[0-9a-f]+ <[^>]+> fe500aa0 vselvs.f32 s1, s1, s1
10 0[0-9a-f]+ <[^>]+> fe2ffa0f vselge.f32 s30, s30, s30
11 0[0-9a-f]+ <[^>]+> fe7ffaaf vselgt.f32 s31, s31, s31
16 0[0-9a-f]+ <[^>]+> fe800a00 vmaxnm.f32 s0, s0, s0
17 0[0-9a-f]+ <[^>]+> fec00aa0 vmaxnm.f32 s1, s1, s1
18 0[0-9a-f]+ <[^>]+> fe8ffa0f vmaxnm.f32 s30, s30, s30
19 0[0-9a-f]+ <[^>]+> fecffaaf vmaxnm.f32 s31, s31, s31
24 0[0-9a-f]+ <[^>]+> fe800a40 vminnm.f32 s0, s0, s0
25 0[0-9a-f]+ <[^>]+> fec00ae0 vminnm.f32 s1, s1, s
[all...] |
| vfp1xD_t2.d | 11 0+004 <[^>]*> eeb4 0ac0 (vcmpe\.f32|fcmpes) s0, s0
12 0+008 <[^>]*> eeb5 0ac0 (vcmpe\.f32 s0, #0.0|fcmpezs s0)
13 0+00c <[^>]*> eeb4 0a40 (vcmp\.f32|fcmps) s0, s0
14 0+010 <[^>]*> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0)
15 0+014 <[^>]*> eeb0 0ac0 (vabs\.f32|fabss) s0, s0
16 0+018 <[^>]*> eeb0 0a40 (vmov\.f32|fcpys) s0, s0
17 0+01c <[^>]*> eeb1 0a40 (vneg\.f32|fnegs) s0, s0
18 0+020 <[^>]*> eeb1 0ac0 (vsqrt\.f32|fsqrts) s0, s0
19 0+024 <[^>]*> ee30 0a00 (vadd\.f32|fadds) s0, s0, s0
20 0+028 <[^>]*> ee80 0a00 (vdiv\.f32|fdivs) s0, s0, s
[all...] |
| vfpv3-const-conv.d | 8 0[0-9a-f]+ <[^>]+> eef08a04 (vmov\.f32|fconsts) s17, #4
9 0[0-9a-f]+ <[^>]+> eeba9a05 (vmov\.f32|fconsts) s18, #165.*
10 0[0-9a-f]+ <[^>]+> eef49a00 (vmov\.f32|fconsts) s19, #64.*
14 0[0-9a-f]+ <[^>]+> eefa8a63 (vcvt\.f32\.s16 s17, s17, #9|fshtos s17, #9)
16 0[0-9a-f]+ <[^>]+> eefa8aeb (vcvt\.f32\.s32 s17, s17, #9|fsltos s17, #9)
18 0[0-9a-f]+ <[^>]+> eefb8a63 (vcvt\.f32\.u16 s17, s17, #9|fuhtos s17, #9)
20 0[0-9a-f]+ <[^>]+> eefb8aeb (vcvt\.f32\.u32 s17, s17, #9|fultos s17, #9)
22 0[0-9a-f]+ <[^>]+> eefe9a64 (vcvt\.s16\.f32 s19, s19, #7|ftoshs s19, #7)
24 0[0-9a-f]+ <[^>]+> eefe9aec (vcvt\.s32\.f32 s19, s19, #7|ftosls s19, #7)
26 0[0-9a-f]+ <[^>]+> eeff9a64 (vcvt\.u16\.f32 s19, s19, #7|ftouhs s19, #7
[all...] |
| /external/llvm/test/MC/ARM/ |
| neon-reciprocal-encoding.s | 7 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3]
8 vrecpe.f32 d16, d16
9 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3]
10 vrecpe.f32 q8, q8
11 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2]
12 vrecps.f32 d16, d16, d17
13 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2]
14 vrecps.f32 q8, q8, q9
19 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3]
20 vrsqrte.f32 d16, d1
[all...] |
| neont2-reciprocal-encoding.s | 9 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x05]
10 vrecpe.f32 d16, d16
11 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x05]
12 vrecpe.f32 q8, q8
13 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x0f]
14 vrecps.f32 d16, d16, d17
15 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x0f]
16 vrecps.f32 q8, q8, q9
21 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x05]
22 vrsqrte.f32 d16, d1
[all...] |
| invalid-fp-armv8.s | 10 vsel.f32 s3, s4, s6
12 vselne.f32 s3, s4, s6
14 vselmi.f32 s3, s4, s6
16 vselpl.f32 s3, s4, s6
18 vselvc.f32 s3, s4, s6
20 vselcs.f32 s3, s4, s6
22 vselcc.f32 s3, s4, s6
24 vselhs.f32 s3, s4, s6
26 vsello.f32 s3, s4, s6
28 vselhi.f32 s3, s4, s
[all...] |
| neon-vcvt-fp16.s | 6 @ CHECK-FP16: vcvtt.f32.f16 s7, s1 @ encoding: [0xe0,0x3a,0xf2,0xee]
8 vcvtt.f32.f16 s7, s1
9 @ CHECK-FP16: vcvtt.f16.f32 s1, s7 @ encoding: [0xe3,0x0a,0xf3,0xee]
11 vcvtt.f16.f32 s1, s7
13 @ CHECK-FP16: vcvtb.f32.f16 s7, s1 @ encoding: [0x60,0x3a,0xf2,0xee]
15 vcvtb.f32.f16 s7, s1
16 @ CHECK-FP16: vcvtb.f16.f32 s1, s7 @ encoding: [0x63,0x0a,0xf3,0xee]
18 vcvtb.f16.f32 s1, s7
|
| vfp4.s | 13 @ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee]
14 @ THUMB: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a]
15 @ THUMB_V7EM: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a]
16 vfma.f32 s2, s4, s0
18 @ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2]
19 @ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c]
21 @ THUMB_V7EM-ERRORS-NEXT: vfma.f32 d16, d18, d17
22 vfma.f32 d16, d18, d17
24 @ ARM: vfma.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x08,0xf2]
25 @ THUMB: vfma.f32 q2, q4, q0 @ encoding: [0x08,0xef,0x50,0x4c
[all...] |
| directive-arch_extension-simd.s | 19 vmaxnm.f32 s0, s0, s0
21 vminnm.f32 s0, s0, s0
29 vcvta.s32.f32 s0, s0
31 vcvta.u32.f32 s0, s0
37 vcvtn.s32.f32 s0, s0
39 vcvtn.u32.f32 s0, s0
45 vcvtp.s32.f32 s0, s0
47 vcvtp.u32.f32 s0, s0
53 vcvtm.s32.f32 s0, s0
55 vcvtm.u32.f32 s0, s
[all...] |
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_format_r11g11b10f.h | 53 } f32 = {val}; local
58 int sign = (f32.ui >> 16) & 0x8000;
60 int exponent = ((f32.ui >> 23) & 0xff) - 127;
61 int mantissa = f32.ui & 0x007fffff;
102 } f32; local
107 f32.f = 0.0;
112 f32.f = scale * mantissa;
116 f32.ui = F32_INFINITY | mantissa;
128 f32.f = scale * decimal;
131 return f32.f
139 } f32 = {val}; local
188 } f32; local
[all...] |
| /bionic/libm/arm/ |
| sqrt.S | 43 vmov.f32 s0, r0
44 vsqrt.f32 s0, s0
45 vmov.f32 r0, s0
|
| /external/compiler-rt/lib/builtins/arm/ |
| fixsfsivfp.S | 23 vcvt.s32.f32 s15, s15 // convert single to 32-bit int into s15
|
| fixunssfsivfp.S | 24 vcvt.u32.f32 s15, s15 // convert single to 32-bit unsigned into s15
|
| floatsisfvfp.S | 23 vcvt.f32.s32 s15, s15 // convert 32-bit int in s15 to float in s15
|
| floatunssisfvfp.S | 23 vcvt.f32.u32 s15, s15 // convert 32-bit int in s15 to float in s15
|
