| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| DalvInsnList.java | 204 (insn.getOpcode().getFamily() == DalvOps.INVOKE_STATIC);
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| DalvInsnList.java | 204 (insn.getOpcode().getFamily() == Opcodes.INVOKE_STATIC);
|
| /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| SymbolManager.h | 358 BinaryOperator::Opcode getOpcode() const { return Op; }
393 Profile(ID, LHS, getOpcode(), RHS, getType());
428 Profile(ID, LHS, getOpcode(), RHS, getType());
462 Profile(ID, LHS, getOpcode(), RHS, getType());
|
| /external/clang/lib/AST/ |
| ExprClassification.cpp | 218 switch (cast<UnaryOperator>(E)->getOpcode()) {
525 if (E->getOpcode() == BO_Comma)
531 if (E->getOpcode() == BO_PtrMemD)
539 if (E->getOpcode() == BO_PtrMemI)
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| CStringSyntaxChecker.cpp | 114 if (BE->getOpcode() == BO_Sub) {
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| DalvInsnList.java | 205 (insn.getOpcode().getFamily() == Opcodes.INVOKE_STATIC);
|
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 159 unsigned getOpcode() const { return Opcode; }
|
| /external/llvm/lib/CodeGen/ |
| DeadMachineInstructionElim.cpp | 63 if (MI->getOpcode() == TargetOpcode::LOCAL_ESCAPE)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 54 switch (N->getOpcode()) {
[all...] |
| ResourcePriorityQueue.cpp | 85 switch (ScegN->getOpcode()) {
122 switch (ScegN->getOpcode()) {
453 switch (N->getOpcode()) {
560 switch(N->getOpcode()) {
|
| SelectionDAGISel.cpp | 592 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
690 if (N->getOpcode() != ISD::CopyToReg)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 378 MII->getOpcode() == AArch64::DBG_VALUE ||
379 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
380 MII->getOpcode() == TargetOpcode::STACKMAP)
451 switch (MI->getOpcode()) {
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRLiveRanges.cpp | 165 if (NCDTerm != NCD->end() && NCDTerm->getOpcode() == AMDGPU::SI_ELSE) {
|
| SIRegisterInfo.cpp | 220 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
270 switch (MI->getOpcode()) {
277 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
310 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 90 unsigned getOpcode(int Op) const;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 90 int Opc = MI->getOpcode();
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCELFStreamer.cpp | 43 if (MCK.getOpcode() != Hexagon::BUNDLE) {
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 130 if (MI.getOpcode() == MSP430::ADD16ri) {
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 186 unsigned Opcode = Node->getOpcode();
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXReplaceImageHandles.cpp | 142 switch (TexHandleDef.getOpcode()) {
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 85 unsigned Opcode = MI->getOpcode();
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInfo.cpp | 70 switch (MI.getOpcode()) {
|
| /external/llvm/lib/Transforms/Scalar/ |
| SpeculativeExecution.cpp | 173 switch (Operator::getOpcode(I)) {
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 60 switch (MI->getOpcode()) {
124 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
138 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
247 switch (Op.getOpcode()) {
271 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
325 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
328 } // end switch(Op.getOpcode())
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/dexbacked/instruction/ |
| DexBackedInstruction.java | 56 @Nonnull public Opcode getOpcode() { return opcode; }
|
