| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 141 SDValue N0 = N.getOperand(0);
207 if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
208 !MatchAddress(N.getNode()->getOperand(1), AM))
211 if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
212 !MatchAddress(N.getNode()->getOperand(0), AM))
221 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
225 if (!MatchAddress(N.getOperand(0), AM) &&
229 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
418 Node->getOperand(0), Node->getOperand(1)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 91 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
94 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
99 Base = Addr.getOperand(0);
106 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
107 Base = Addr.getOperand(1);
108 Offset = Addr.getOperand(0).getOperand(0);
111 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
112 Base = Addr.getOperand(0);
113 Offset = Addr.getOperand(1).getOperand(0)
[all...] |
| DelaySlotFiller.cpp | 254 const MachineOperand &MO = candidate->getOperand(i);
288 const MachineOperand &Reg = MI->getOperand(0);
293 const MachineOperand &RegOrImm = MI->getOperand(1);
309 const MachineOperand &MO = MI->getOperand(i);
353 const MachineOperand &MO = I->getOperand(structSizeOpNum);
369 unsigned reg = AddMI->getOperand(0).getReg();
382 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
397 unsigned reg = OrMI->getOperand(0).getReg();
403 && OrMI->getOperand(1).getReg() != SP::G0
404 && OrMI->getOperand(2).getReg() != SP::G0
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 100 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
109 int64_t Sampler = MI.getOperand(14).getImm();
112 MI.getOperand(2).getImm(),
113 MI.getOperand(3).getImm(),
114 MI.getOperand(4).getImm(),
115 MI.getOperand(5).getImm()
118 MI.getOperand(6).getImm() & 0x1F,
119 MI.getOperand(7).getImm() & 0x1F,
120 MI.getOperand(8).getImm() & 0x1F
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 92 MI->getOperand(1).isBlockAddress()) {
93 int DestReg = MI->getOperand(0).getReg();
94 MachineOperand &Symbol = MI->getOperand (1);
108 int DestReg = MI->getOperand(0).getReg();
114 APFloat Val = MI->getOperand(1).getFPImm()->getValueAPF();
118 ImmValue = MI->getOperand(1).getImm();
127 int DestReg = MI->getOperand(0).getReg();
133 APFloat Val = MI->getOperand(1).getFPImm()->getValueAPF();
137 ImmValue = MI->getOperand(1).getImm();
|
| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 73 MachineOperand &MO = MI->getOperand(i);
82 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
83 MI->getOperand(1).isImm() &&
84 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
85 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
87 unsigned DstReg = MI->getOperand(0).getReg();
88 unsigned InsReg = MI->getOperand(2).getReg();
89 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?")
[all...] |
| OptimizePHIs.cpp | 92 unsigned DstReg = MI->getOperand(0).getReg();
104 unsigned SrcReg = MI->getOperand(i).getReg();
111 !SrcMI->getOperand(0).getSubReg() &&
112 !SrcMI->getOperand(1).getSubReg() &&
113 TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
114 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
135 unsigned DstReg = MI->getOperand(0).getReg();
170 unsigned OldReg = MI->getOperand(0).getReg();
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 74 int64_t Imm = MI->getOperand(Op).getImm();
114 int64_t Imm = MI->getOperand(Op).getImm();
130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
144 const MCOperand &Op = MI->getOperand(OpNo);
164 const MCOperand &Op = MI->getOperand(OpNo);
189 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
190 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
191 const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
192 const MCOperand &SegReg = MI->getOperand(Op + X86::AddrSegmentReg);
219 unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm()
[all...] |
| X86IntelInstPrinter.cpp | 56 int64_t Imm = MI->getOperand(Op).getImm();
96 int64_t Imm = MI->getOperand(Op).getImm();
112 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
125 const MCOperand &Op = MI->getOperand(OpNo);
146 const MCOperand &Op = MI->getOperand(OpNo);
159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
160 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
162 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
163 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg)
[all...] |
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCCodeEmitter.cpp | 151 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
152 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
161 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
162 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
171 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
172 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
173 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI);
182 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI);
183 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
184 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 177 const MachineOperand &MO = MI->getOperand(OpNum);
249 if (MI->getOperand(OpNum).isReg()) {
251 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
257 if (!MI->getOperand(OpNum).isImm())
259 O << MI->getOperand(OpNum).getImm();
266 if (MI->getOperand(OpNum).isReg()) {
267 unsigned Reg = MI->getOperand(OpNum).getReg();
281 if (!MI->getOperand(OpNum).isImm())
283 O << ~(MI->getOperand(OpNum).getImm());
286 if (!MI->getOperand(OpNum).isImm()
[all...] |
| A15SDOptimizer.cpp | 170 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
172 SReg = MI->getOperand(1).getReg();
198 MachineOperand &MO = MI->getOperand(i);
221 MachineOperand &MODef = Def->getOperand(j);
254 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
258 unsigned DPRReg = MI->getOperand(1).getReg();
259 unsigned SPRReg = MI->getOperand(2).getReg();
262 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
263 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
275 EC->getOperand(1).getSubReg() == ARM::ssub_0)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPeephole.cpp | 82 auto &Op = Root.getOperand(1);
97 auto &BaseAddrOp = GenericAddrDef->getOperand(1);
110 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
114 Root.getOperand(0).getReg())
116 .addOperand(Prev.getOperand(2));
121 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
|
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 32 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
37 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
42 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
47 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
52 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
57 if (MI->getOperand(OpNo).getImm())
63 if (MI->getOperand(OpNo).getImm())
69 if (MI->getOperand(OpNo).getImm())
75 if (MI->getOperand(OpNo).getImm()) {
83 uint16_t Imm = MI->getOperand(OpNo).getImm()
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 35 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo));
161 computeKnownBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth + 1,
163 computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth + 1,
171 return I->getOperand(0);
174 return I->getOperand(1);
185 computeKnownBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth + 1,
187 computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth + 1,
195 return I->getOperand(0);
198 return I->getOperand(1);
204 return I->getOperand(0)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 50 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
51 N->getOperand(1));
180 Base = Addr.getOperand(0);
181 Offset = Addr.getOperand(1);
191 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
196 (Addr.getOperand(0))) {
201 Base = Addr.getOperand(0);
217 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
218 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
219 SDValue Opnd0 = Addr.getOperand(1).getOperand(0)
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonInstPrinter.cpp | 62 printInstruction(MCI.getOperand(1).getInst(), OS);
65 printInstruction(MCI.getOperand(0).getInst(), OS);
94 MCOperand const &MO = MI->getOperand(OpNo);
116 O << MI->getOperand(OpNo).getImm();
121 O << -MI->getOperand(OpNo).getImm();
132 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
142 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
152 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
162 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
176 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression")
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 156 const MCOperand &MO = MI.getOperand(OpNo);
168 const MCOperand &MO = MI.getOperand(OpNo);
181 const MCOperand &MO = MI.getOperand(OpNo);
194 const MCOperand &MO = MI.getOperand(OpNo);
206 const MCOperand &MO = MI.getOperand(OpNo);
220 assert(MI.getOperand(OpNo+1).isReg());
221 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
223 const MCOperand &MO = MI.getOperand(OpNo);
239 assert(MI.getOperand(OpNo+1).isReg());
240 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 307 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
317 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
368 Op.getNode()->getOperand(0)),
370 Op.getNode()->getOperand(1)));
435 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
438 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
441 return TLO.CombineTo(Op, Op.getOperand(0));
448 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
452 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
460 return TLO.CombineTo(Op, Op.getOperand(0))
[all...] |
| LegalizeIntegerTypes.cpp | 169 SDValue Op = SExtPromotedInteger(N->getOperand(0));
171 Op.getValueType(), Op, N->getOperand(1));
176 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
178 Op.getValueType(), Op, N->getOperand(1));
195 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
211 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
222 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
230 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
231 SDValue Op3 = GetPromotedInteger(N->getOperand(3))
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCEarlyReturn.cpp | 83 if (J->getOperand(0).getMBB() == &ReturnMBB) {
95 if (J->getOperand(2).getMBB() == &ReturnMBB) {
99 .addImm(J->getOperand(0).getImm())
100 .addReg(J->getOperand(1).getReg())
109 if (J->getOperand(1).getMBB() == &ReturnMBB) {
115 .addReg(J->getOperand(0).getReg())
129 if (J->getOperand(i).isMBB() &&
130 J->getOperand(i).getMBB() == &ReturnMBB)
|
| /external/llvm/lib/Analysis/ |
| PHITransAddr.cpp | 35 isa<ConstantInt>(Inst->getOperand(1)))
40 // cerr << "OP:\t\t\t\t" << *PtrInst->getOperand(0);
83 if (!VerifySubExpr(I->getOperand(i), InstInputs))
140 if (Instruction *Op = dyn_cast<Instruction>(I->getOperand(i)))
182 if (Instruction *Op = dyn_cast<Instruction>(Inst->getOperand(i)))
192 Value *PHIIn = PHITranslateSubExpr(Cast->getOperand(0), CurBB, PredBB, DT);
194 if (PHIIn == Cast->getOperand(0))
221 Value *GEPOp = PHITranslateSubExpr(GEP->getOperand(i), CurBB, PredBB, DT);
224 AnyChanged |= GEPOp != GEP->getOperand(i);
256 isa<ConstantInt>(Inst->getOperand(1)))
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 66 const MCOperand &Op0 = MI->getOperand(0);
67 const MCOperand &Op1 = MI->getOperand(1);
68 const MCOperand &Op2 = MI->getOperand(2);
69 const MCOperand &Op3 = MI->getOperand(3);
160 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
161 const MCOperand &Op2 = MI->getOperand(2);
162 int ImmR = MI->getOperand(3).getImm();
163 int ImmS = MI->getOperand(4).getImm();
203 MI->getOperand(1).isExpr()) {
209 O << getRegisterName(MI->getOperand(0).getReg()) << ", #"
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 215 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()) ||
222 NewMI.addOperand(MI->getOperand(i));
231 MI->getOperand(0).getReg(),
232 MI->getOperand(1).getReg());
240 MI->getOperand(0).getReg(),
241 MI->getOperand(1).getReg());
249 MI->getOperand(0).getReg(),
250 MI->getOperand(1).getReg());
256 unsigned maskedRegister = MI->getOperand(0).getReg();
264 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg()
[all...] |
| /external/llvm/lib/Target/BPF/InstPrinter/ |
| BPFInstPrinter.cpp | 55 const MCOperand &Op = MI->getOperand(OpNo);
68 const MCOperand &RegOp = MI->getOperand(OpNo);
69 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
83 const MCOperand &Op = MI->getOperand(OpNo);
|
