| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 254 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
301 const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
[all...] |
| Mips16InstrInfo.cpp | 37 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
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| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 114 computeRegisterProperties(Subtarget->getRegisterInfo());
642 Subtarget->getRegisterInfo()->getFrameRegister(DAG.getMachineFunction());
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| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 228 const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo();
265 MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(),
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfDebug.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| IfConversion.cpp | 282 TRI = ST.getRegisterInfo();
296 BFChange = BF.OptimizeFunction(MF, TII, ST.getRegisterInfo(),
429 BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(),
[all...] |
| CriticalAntiDepBreaker.cpp | 34 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
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| ExecutionDepsFix.cpp | 724 TRI = MF->getSubtarget().getRegisterInfo();
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| MachineCSE.cpp | 715 TRI = MF.getSubtarget().getRegisterInfo();
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| MachineSink.cpp | 265 TRI = MF.getSubtarget().getRegisterInfo();
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| ScheduleDAG.cpp | 40 TRI(mf.getSubtarget().getRegisterInfo()), MF(mf),
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| MachineBasicBlock.cpp | 285 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
864 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineRegisterInfo.h | 120 return MF->getSubtarget().getRegisterInfo();
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 142 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
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| ResourcePriorityQueue.cpp | 47 TRI = STI.getRegisterInfo();
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| /external/llvm/lib/MC/MCParser/ |
| COFFAsmParser.cpp | 753 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
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| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 242 MF->getSubtarget<AArch64Subtarget>().getRegisterInfo();
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| AArch64InstrInfo.cpp | 618 const TargetRegisterInfo *TRI = &getRegisterInfo();
712 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
869 const TargetRegisterInfo *TRI = &getRegisterInfo();
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 208 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
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| /external/llvm/lib/Target/AMDGPU/ |
| SILowerControlFlow.cpp | 470 static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
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| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 690 TRI = STI.getRegisterInfo();
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 262 const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
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| HexagonGenPredicate.cpp | 483 TRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 349 const TargetRegisterInfo *TRI = &getRegisterInfo();
|
