| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips4-fp.d | 26 [0-9a-f]+ <[^>]*> movt a0,a1,\$fcc4
27 [0-9a-f]+ <[^>]*> movt.d \$f4,\$f6,\$fcc0
28 [0-9a-f]+ <[^>]*> movt.s \$f4,\$f6,\$fcc0
|
| set-arch.s | 57 movt $4,$5,$fcc4
58 movt.d $f4,$f6,$fcc0
59 movt.s $f4,$f6,$fcc0
132 movt.ps $f28, $f30, $fcc4
|
| micromips@mips4-fp.d | 31 [0-9a-f]+ <[^>]*> 5485 897b movt a0,a1,\$fcc4
32 [0-9a-f]+ <[^>]*> 5486 0260 movt\.d \$f4,\$f6,\$fcc0
33 [0-9a-f]+ <[^>]*> 5486 0060 movt\.s \$f4,\$f6,\$fcc0
|
| mips4-fp.l | 16 .*:19: Error: opcode not supported on this processor: .* \(.*\) `movt \$4,\$5,\$fcc4'
17 .*:20: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
18 .*:21: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
|
| r6-removed.s | 154 movt $10,$11,$fcc2
155 movt.s $f20,$f21,$fcc2
156 movt.d $f20,$f22,$fcc2
157 movt.ps $f20,$f22,$fcc2
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips5.s | 22 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
23 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
24 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32.s | 20 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
21 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/ARM/ |
| elf-movt.s | 12 movt r0, :upper16:GOT-(.LPC0_2+8)
15 @ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+8))
|
| big-endian-arm-fixup.s | 81 movt r0, :upper16:GOT-(movt_label)
|
| coff-relocations.s | 37 movt r0, :upper16:target
42 @ CHECK-ENCODING-NEXT: movt r0, #0
|
| /external/llvm/test/MC/MachO/ARM/ |
| thumb2-movw-fixup.s | 11 movt r2, :upper16:L1
13 movt r12, :upper16:L2
|
| thumb2-movt-fixup.s | 4 movt r3, :upper16:(_wilma-(LPC0_0+4))
|
| static-movt-relocs.s | 6 movt r0, :upper16:(bar + 16)
|
| /external/llvm/test/MC/ARM/Windows/ |
| mov32t-range.s | 19 movt r0, :upper16:.Lerange
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32.s | 31 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
32 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
33 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
35 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips32r2.s | 40 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
42 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
43 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
44 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips4.s | 60 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
61 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
62 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
63 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
64 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 59 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
60 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
61 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
62 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
63 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-arm/ |
| ifunc-2.s | 22 movt r4,#:upper16:\name
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips64.s | 32 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/ExecutionEngine/RuntimeDyld/ARM/ |
| MachO_ARM_PIC_relocations.s | 16 movt r0, :upper16:(foo$non_lazy_ptr-(nextPC+8))
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| archv6t2.s | 39 movt r0, #0
|
| /art/compiler/linker/arm/ |
| relative_patcher_thumb2_test.cc | 148 0xc0, 0xf2, 0x00, 0x00, // MOVT r0, #0 (placeholder)
184 // Distribute the bits of the diff between the MOVW and MOVT:
192 uint32_t movt = 0xf2c00000u | // MOVT r0, #0 (placeholder), local
200 static_cast<uint8_t>(movt >> 16), static_cast<uint8_t>(movt >> 24),
201 static_cast<uint8_t>(movt >> 0), static_cast<uint8_t>(movt >> 8),
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 64 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
65 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
66 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
67 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
68 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 63 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
64 movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
65 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
66 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
67 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
