| /external/llvm/test/MC/Mips/ |
| micromips-fpu-instructions.s | 62 # CHECK-EL: movt.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x00]
63 # CHECK-EL: movt.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x02]
127 # CHECK-EB: movt.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x60]
128 # CHECK-EB: movt.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x60]
188 movt.s $f4, $f6, $fcc0
189 movt.d $f4, $f6, $fcc0
|
| mips-fpu-instructions.s | 164 # CHECK: movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00]
165 # CHECK: movt $4, $5, $fcc4 # encoding: [0x01,0x20,0xb1,0x00]
199 movt $2, $1, $fcc0
200 movt $4, $5, $fcc4
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mcore/ |
| allinsn.s | 95 test movt "r8, r9"
|
| allinsn.d | 251 0+0a6 <movt>:
252 a6: 0298 movt r8, r9
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips5-fp.s | 47 movt.ps $f28, $f30, $fcc4
|
| set-arch.d | 18 00000028 <[^>]*> 018d5801 movt t3,t4,\$fcc3
45 00000094 <[^>]*> 00b12001 movt a0,a1,\$fcc4
46 00000098 <[^>]*> 46213111 movt\.d \$f4,\$f6,\$fcc0
47 0000009c <[^>]*> 46013111 movt\.s \$f4,\$f6,\$fcc0
107 0000018c <[^>]*> 46d1f711 movt\.ps \$f28,\$f30,\$fcc4
|
| mips5-fp.d | 53 0+00ac <[^>]*> 46d1f711 movt\.ps \$f28,\$f30,\$fcc4
|
| r6-removed.l | 153 .*:154: Error: opcode not supported on this processor: .* \(.*\) `movt \$10,\$11,\$fcc2'
154 .*:155: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f20,\$f21,\$fcc2'
155 .*:156: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f20,\$f22,\$fcc2'
156 .*:157: Error: opcode not supported on this processor: .* \(.*\) `movt.ps \$f20,\$f22,\$fcc2'
|
| sb1-ext-mdmx.s | 18 movt.l $v1, $v12, $fcc5
|
| micromips@mips5-fp.d | 54 [0-9a-f]+ <[^>]*> 579e 8460 movt\.ps \$f28,\$f30,\$fcc4
|
| sb1-ext-mdmx.d | 12 0+0008 <[^>]*> 46b56051 movt\.l \$f1,\$f12,\$fcc5
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| archv6t2.d | 38 0+78 <[^>]+> e3400000 movt r0, #0
|
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 107 movt $zero,$s4,$fcc5
108 movt.d $f0,$f2,$fcc0
109 movt.s $f30,$f2,$fcc1
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips5-wrong-error.s | 35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips5-wrong-error.s | 35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips5-wrong-error.s | 35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips5-wrong-error.s | 35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| valid.s | 163 movt $zero,$s4,$fcc5
164 movt.d $f0,$f2,$fcc0
165 movt.s $f30,$f2,$fcc1
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips5-wrong-error.s | 37 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/ARM/ |
| thumb2-diagnostics.s | 81 movt r0, foo2
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 746 COMPARE(movt(a0, a1, 1),
747 "00a52001 movt a0, a1, 1");
748 COMPARE(movt(s0, s1, 2),
749 "02298001 movt s0, s1, 2");
750 COMPARE(movt(t2, t3, 3),
751 "016d5001 movt t2, t3, 3");
752 COMPARE(movt(v0, v1, 7),
753 "007d1001 movt v0, v1, 7");
[all...] |
| test-disasm-mips64.cc | 653 COMPARE(movt(a0, a1, 1),
654 "00a52001 movt a0, a1, 1");
655 COMPARE(movt(s0, s1, 2),
656 "02298001 movt s0, s1, 2");
657 COMPARE(movt(a6, a7, 3),
658 "016d5001 movt a6, a7, 3");
659 COMPARE(movt(v0, v1, 7),
660 "007d1001 movt v0, v1, 7");
[all...] |
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 122 movt $zero,$s4,$fcc5
123 movt.d $f0,$f2,$fcc0
124 movt.s $f30,$f2,$fcc1
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 122 movt $zero,$s4,$fcc5
123 movt.d $f0,$f2,$fcc0
124 movt.s $f30,$f2,$fcc1
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 123 movt $zero,$s4,$fcc5
124 movt.d $f0,$f2,$fcc0
125 movt.s $f30,$f2,$fcc1
|
