/external/compiler-rt/test/builtins/Unit/arm/ |
call_apsr.S | 28 mrs r0, apsr 41 mrs r0, apsr
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
mrs-msr-thumb-v7-m-bad.s | 5 mrs r4, cpsr 6 mrs r5, spsr
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arm6.d | 8 0+00 <[^>]+> e10f8000 ? mrs r8, CPSR 9 0+04 <[^>]+> e14f2000 ? mrs r2, SPSR 14 0+18 <[^>]+> e10f8000 ? mrs r8, CPSR 15 0+1c <[^>]+> e14f2000 ? mrs r2, SPSR
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mrs-msr-arm-v7-a-bad.d | 1 # name: MRS/MSR negative test, architecture v7-A, ARM mode 2 # error-output: mrs-msr-arm-v7-a-bad.l
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mrs-msr-arm-v7-a-bad.l | 2 [^:]*:5: Error: 'APSR', 'CPSR' or 'SPSR' expected -- `mrs r4,apsr_nzcvq' 3 [^:]*:6: Error: selected processor does not support requested special purpose register -- `mrs r5,iapsr'
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mrs-msr-thumb-v7-m-bad.d | 1 # name: MRS/MSR negative test, architecture v7-M, Thumb mode 2 # error-output: mrs-msr-thumb-v7-m-bad.l
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mrs-msr-arm-v6.d | 2 #name: MRS/MSR test, architecture v6, ARM mode 8 0+00 <[^>]*> e10f4000 mrs r4, CPSR 9 0+04 <[^>]*> e10f5000 mrs r5, CPSR 10 0+08 <[^>]*> e14f6000 mrs r6, SPSR
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mrs-msr-arm-v7-a.d | 2 #name: MRS/MSR test, architecture v7-A, ARM mode 8 0+00 <[^>]*> e10f4000 mrs r4, CPSR 9 0+04 <[^>]*> e10f5000 mrs r5, CPSR 10 0+08 <[^>]*> e14f6000 mrs r6, SPSR
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mrs-msr-thumb-v6t2.d | 2 #name: MRS/MSR test, architecture v6t2, Thumb mode 10 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR 11 0+04 <[^>]*> f3ef 8500 mrs r5, CPSR 12 0+08 <[^>]*> f3ff 8600 mrs r6, SPSR
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mrs-msr-thumb-v7-m.d | 2 #name: MRS/MSR test, architecture v7-M, Thumb mode 10 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR 11 0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR 12 0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
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mrs-msr-thumb-v7e-m.d | 2 #name: MRS/MSR test, architecture v7e-M, Thumb mode 10 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR 11 0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR 12 0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
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arch7.d | 50 0+0a0 <[^>]*> f3ef 8000 mrs r0, (CPSR|APSR) 51 0+0a4 <[^>]*> f3ef 8001 mrs r0, IAPSR 52 0+0a8 <[^>]*> f3ef 8002 mrs r0, EAPSR 53 0+0ac <[^>]*> f3ef 8003 mrs r0, PSR 54 0+0b0 <[^>]*> f3ef 8005 mrs r0, IPSR 55 0+0b4 <[^>]*> f3ef 8006 mrs r0, EPSR 56 0+0b8 <[^>]*> f3ef 8007 mrs r0, IEPSR 57 0+0bc <[^>]*> f3ef 8008 mrs r0, MSP 58 0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP 59 0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMAS [all...] |
archv6m.s | 10 mrs r2, iapsr
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thumb-w-good.s | 6 mrs.w r0, apsr
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/external/llvm/test/MC/AArch64/ |
basic-a64-instructions.s | [all...] |
/external/llvm/test/MC/ARM/ |
thumbv7m.s | 10 @ MRS 13 mrs r0, basepri 14 mrs r0, basepri_max 15 mrs r0, faultmask 17 @ CHECK: mrs r0, basepri @ encoding: [0xef,0xf3,0x11,0x80] 18 @ CHECK: mrs r0, basepri_max @ encoding: [0xef,0xf3,0x12,0x80] 19 @ CHECK: mrs r0, faultmask @ encoding: [0xef,0xf3,0x13,0x80] 34 @ CHECK-V6M-NEXT: mrs r0, basepri 36 @ CHECK-V6M-NEXT: mrs r0, basepri_max 38 @ CHECK-V6M-NEXT: mrs r0, faultmas [all...] |
thumb2-mclass.s | 10 @ MRS 13 mrs r0, apsr 14 mrs r0, iapsr 15 mrs r0, eapsr 16 mrs r0, xpsr 17 mrs r0, ipsr 18 mrs r0, epsr 19 mrs r0, iepsr 20 mrs r0, msp 21 mrs r0, ps [all...] |
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
msr.s | 33 mrs x0, daif
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/toolchain/binutils/binutils-2.25/ld/testsuite/ld-aarch64/ |
tls-relax-ie-le.s | 5 mrs x1, tpidr_el0
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tls-relax-all.d | 11 +10018: d53bd041 mrs x1, tpidr_el0 18 +10034: d53bd042 mrs x2, tpidr_el0 24 +1004c: d53bd041 mrs x1, tpidr_el0 30 +10064: d53bd041 mrs x1, tpidr_el0 34 +10074: d53bd042 mrs x2, tpidr_el0
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tls-relax-gd-ie.d | 7 +10008: d53bd041 mrs x1, tpidr_el0
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tls-relax-gd-le.d | 7 +10008: d53bd041 mrs x1, tpidr_el0
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tls-relax-gdesc-ie.d | 9 +10010: d53bd041 mrs x1, tpidr_el0
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tls-relax-gdesc-le.d | 9 +10010: d53bd041 mrs x1, tpidr_el0
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tls-relax-ie-le-3.d | 5 +10000: d53bd042 mrs x2, tpidr_el0
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