| /external/libunwind/src/ia64/ |
| Gparser.c | 50 print_error ("libunwind: cannot stack reg state!\n");
155 set_reg (struct ia64_reg_info *reg, enum ia64_where where, int when,
158 reg->val = val;
159 reg->where = where;
160 if (reg->when == IA64_WHEN_NEVER)
161 reg->when = when;
168 struct ia64_reg_info *reg; local
170 for (reg = hi; reg >= lo; --reg)
185 struct ia64_reg_info *reg; local
202 struct ia64_reg_info *reg; local
476 struct ia64_reg_info *reg = sr->curr.reg + regnum; local
[all...] |
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_build.c | 1061 const struct tgsi_full_dst_register *reg = &full_inst->Dst[i]; local
1070 reg->Register.File,
1071 reg->Register.WriteMask,
1072 reg->Register.Indirect,
1073 reg->Register.Dimension,
1074 reg->Register.Index,
1078 if( reg->Register.Indirect ) {
1087 reg->Indirect.File,
1088 reg->Indirect.SwizzleX,
1089 reg->Indirect.SwizzleY
1143 const struct tgsi_full_src_register *reg = &full_inst->Src[i]; local
[all...] |
| tgsi_ureg.h | [all...] |
| /bionic/libc/arch-x86_64/bionic/ |
| setjmp.S | 69 .macro m_mangle_registers reg
71 xorq \reg,%rbx
72 xorq \reg,%rbp
73 xorq \reg,%r12
74 xorq \reg,%r13
75 xorq \reg,%r14
76 xorq \reg,%r15
77 xorq \reg,%rsp
78 xorq \reg,%r11
82 .macro m_unmangle_registers reg
[all...] |
| /external/libunwind/src/sh/ |
| Gresume.c | 126 int reg; local
130 for (reg = 0; reg <= UNW_REG_LAST; ++reg)
132 Debug (16, "copying %s %d\n", unw_regname (reg), reg);
133 if (unw_is_fpreg (reg))
135 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0)
136 as->acc.access_fpreg (as, reg, &fpval, 1, arg);
140 if (tdep_access_reg (c, reg, &val, 0) >= 0
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_build_util.cpp | 57 unsigned int pos = u32Hash(imm->reg.data.u32);
185 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(src->reg.size));
188 insn->getDef(0)->reg.data.id = id;
198 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(dst->reg.size));
202 insn->getSrc(0)->reg.data.id = id;
228 insn->setType((dst->reg.file == FILE_PREDICATE ||
229 dst->reg.file == FILE_FLAGS) ? TYPE_U8 : ty, ty);
237 if (dst->reg.file == FILE_FLAGS)
278 return mkOp2(OP_UNION, typeOfSize(dst->reg.size), dst, def0, def1);
288 if (val->reg.file == FILE_IMMEDIATE
339 LValue *reg = new_LValue(func, f); local
345 LValue *reg = new_LValue(func, f); local
[all...] |
| nv50_ir_print.cpp | 325 int idx = join->reg.data.id >= 0 ? join->reg.data.id : id;
326 char p = join->reg.data.id >= 0 ? '$' : '%';
330 switch (reg.file) {
333 if (reg.size == 2) {
341 if (reg.size == 8) {
344 if (reg.size == 16) {
347 if (reg.size == 12) {
353 if (reg.size == 2)
356 if (reg.size == 4
[all...] |
| /external/valgrind/none/tests/x86/ |
| bt_everything.c | 159 UInt reg; local
193 /*------------------------ REG-L -----------------------*/
196 reg = 0;
203 case 0: c = btsl_reg(reg, bitoff, ®); break;
204 case 1: c = btrl_reg(reg, bitoff, ®); break;
205 case 2: c = btcl_reg(reg, bitoff, ®); break;
206 case 3: c = btl_reg(reg, bitoff, ®); break
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| score-dis.c | 568 long reg;
570 reg = given >> bitstart;
571 reg &= (2 << (bitend - bitstart)) - 1;
573 func (stream, "%s", score_regnames[reg]);
578 long reg;
580 reg = given >> bitstart;
581 reg &= (2 << (bitend - bitstart)) - 1;
583 func (stream, "%ld", reg);
588 long reg;
589 reg = given >> bitstart
567 long reg; local
577 long reg; local
587 long reg; local
609 long reg; local
622 long reg; local
736 long reg; local
789 long reg; local
799 long reg; local
809 long reg; local
829 long reg; local
946 long reg; local
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| radeonsi_pm4.c | 56 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
60 if (reg >= SI_CONFIG_REG_OFFSET && reg <= SI_CONFIG_REG_END) {
62 reg -= SI_CONFIG_REG_OFFSET;
64 } else if (reg >= SI_SH_REG_OFFSET && reg <= SI_SH_REG_END) {
66 reg -= SI_SH_REG_OFFSET;
68 } else if (reg >= SI_CONTEXT_REG_OFFSET && reg <= SI_CONTEXT_REG_END) {
70 reg -= SI_CONTEXT_REG_OFFSET
[all...] |
| /hardware/bsp/intel/peripheral/libupm/src/am2315/ |
| am2315.cpp | 189 AM2315::i2cWriteReg(uint8_t reg, uint8_t* data, uint8_t ilen)
191 uint8_t tdata[16] = { AM2315_WRITE, reg, ilen };
218 (tdata[1] != reg) ||
234 AM2315::i2cReadReg(int reg, uint8_t* data, int ilen)
236 uint8_t tdata[16] = { AM2315_READ, reg, ilen };
273 AM2315::i2cWriteReg_32(int reg, uint32_t ival) {
279 return i2cWriteReg(reg, data, 4);
283 AM2315::i2cWriteReg_16(int reg, uint16_t ival) {
287 return i2cWriteReg(reg, data, 2);
291 AM2315::i2cWriteReg_8(int reg, uint8_t ival)
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_clip_unfilled.c | 53 struct brw_reg e = c->reg.tmp0;
54 struct brw_reg f = c->reg.tmp1;
57 struct brw_reg v0 = byte_offset(c->reg.vertex[0], hpos_offset);
58 struct brw_reg v1 = byte_offset(c->reg.vertex[1], hpos_offset);
59 struct brw_reg v2 = byte_offset(c->reg.vertex[2], hpos_offset);
94 brw_MUL(p, c->reg.dir, c->reg.dir, vec4(e));
114 get_element(c->reg.dir, 2),
151 get_element(c->reg.dir, 2),
162 byte_offset(c->reg.vertex[i]
[all...] |
| /bionic/libc/arch-arm64/bionic/ |
| setjmp.S | 71 .macro m_mangle_registers reg, sp_reg
73 eor x19, x19, \reg
74 eor x20, x20, \reg
75 eor x21, x21, \reg
76 eor x22, x22, \reg
77 eor x23, x23, \reg
78 eor x24, x24, \reg
79 eor x25, x25, \reg
80 eor x26, x26, \reg
81 eor x27, x27, \reg
[all...] |
| /bionic/libc/kernel/uapi/asm-x86/asm/ |
| mtrr.h | 79 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
80 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /development/ndk/platforms/android-21/arch-x86/include/asm/ |
| mtrr.h | 79 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
80 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /development/ndk/platforms/android-21/arch-x86_64/include/asm/ |
| mtrr.h | 79 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
80 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| mtrr.h | 91 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
92 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600RegisterInfo.h | 32 unsigned getHWRegChan(unsigned reg) const;
34 unsigned getHWRegIndex(unsigned Reg) const override;
43 // \returns true if \p Reg can be defined in one ALU caluse and used in another.
44 bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
|
| /external/valgrind/VEX/priv/ |
| host_generic_regs.c | 107 HReg reg = univ->regs[i]; local
108 vassert(!hregIsInvalid(reg));
109 vassert(!hregIsVirtual(reg));
110 vassert(hregIndex(reg) == i);
113 HReg reg = univ->regs[i]; local
114 vassert(hregIsInvalid(reg));
120 /*--- Helpers for recording reg usage (for reg-alloc) ---*/
162 create duplicate entries -- each reg is only mentioned once.
164 void addHRegUse ( HRegUsage* tab, HRegMode mode, HReg reg )
[all...] |
| /external/vixl/examples/ |
| custom-disassembler.h | 49 const CPURegister& reg);
|
| /hardware/bsp/intel/peripheral/libupm/src/adc121c021/ |
| adc121c021.h | 111 * @param reg Register location to write into
115 mraa_result_t writeByte(uint8_t reg, uint8_t byte);
120 * @param reg Register location to write into
124 mraa_result_t writeWord(uint8_t reg, uint16_t word);
129 * @param reg Register location to read from
132 uint8_t readByte(uint8_t reg);
137 * @param reg Register location to read from
140 uint16_t readWord(uint8_t reg);
|
| /hardware/bsp/intel/peripheral/libupm/src/max31723/ |
| max31723.cxx | 79 MAX31723::readRegister (uint8_t reg) {
84 data[0] = reg;
92 MAX31723::writeRegister (uint8_t reg, uint8_t data) {
97 buffer[0] = reg;
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/sysroot/usr/include/asm/ |
| mtrr.h | 83 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
84 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/i386-linux-gnu/asm/ |
| mtrr.h | 83 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
84 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/x86_64-linux-gnu/asm/ |
| mtrr.h | 83 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
84 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
