/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
inst-directive.d | 8 0: 3619194c tbz w12, #3, 2328 <\.text\+0x2328>
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/external/llvm/test/MC/Mips/msa/ |
set-msa-directive.s | 4 # CHECK: addvi.b $w14, $w12, 14 8 # CHECK: subvi.b $w14, $w12, 14 14 addvi.b $w14, $w12, 14 19 subvi.b $w14, $w12, 14
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test_2rf.s | 3 # CHECK: fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e] 10 # CHECK: ffint_s.d $w12, $w15 # encoding: [0x7b,0x3d,0x7b,0x1e] 14 # CHECK: ffql.d $w12, $w13 # encoding: [0x7b,0x35,0x6b,0x1e] 23 # CHECK: frsqrt.w $w12, $w17 # encoding: [0x7b,0x28,0x8b,0x1e] 26 # CHECK: fsqrt.d $w15, $w12 # encoding: [0x7b,0x27,0x63,0xde] 32 # CHECK: ftrunc_s.d $w12, $w27 # encoding: [0x7b,0x23,0xdb,0x1e] 36 fclass.w $w26, $w12 43 ffint_s.d $w12, $w15 47 ffql.d $w12, $w13 56 frsqrt.w $w12, $w1 [all...] |
test_i5.s | 9 # CHECK: ceqi.w $w12, $w1, -1 # encoding: [0x78,0x5f,0x0b,0x07] 11 # CHECK: clei_s.b $w12, $w16, 1 # encoding: [0x7a,0x01,0x83,0x07] 21 # CHECK: clti_s.w $w12, $w12, 11 # encoding: [0x79,0x4b,0x63,0x07] 41 # CHECK: mini_u.w $w11, $w12, 26 # encoding: [0x7a,0xda,0x62,0xc6] 45 # CHECK: subvi.w $w12, $w10, 11 # encoding: [0x78,0xcb,0x53,0x06] 54 ceqi.w $w12, $w1, -1 56 clei_s.b $w12, $w16, 1 66 clti_s.w $w12, $w12, 1 [all...] |
set-msa-directive-bad.s | 5 addvi.b $w14, $w12, 14 # CHECK: error: instruction requires a CPU feature not currently enabled
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test_3r.s | 26 # CHECK: asub_s.d $w13, $w12, $w12 # encoding: [0x7a,0x6c,0x63,0x51] 37 # CHECK: ave_u.w $w11, $w12, $w11 # encoding: [0x7a,0xcb,0x62,0xd0] 54 # CHECK: binsl.d $w23, $w20, $w12 # encoding: [0x7b,0x6c,0xa5,0xcd] 64 # CHECK: bset.h $w14, $w12, $w6 # encoding: [0x7a,0x26,0x63,0x8d] 65 # CHECK: bset.w $w31, $w9, $w12 # encoding: [0x7a,0x4c,0x4f,0xcd] 82 # CHECK: clt_s.d $w7, $w30, $w12 # encoding: [0x79,0x6c,0xf1,0xcf] 102 # CHECK: dpadd_s.w $w10, $w1, $w12 # encoding: [0x79,0x4c,0x0a,0x93] 107 # CHECK: dpsub_s.h $w4, $w11, $w12 # encoding: [0x7a,0x2c,0x59,0x13] 109 # CHECK: dpsub_s.d $w31, $w12, $w28 # encoding: [0x7a,0x7c,0x67,0xd3 [all...] |
test_elm.s | 11 sldi.d $w4, $w12[0] # CHECK: sldi.d $w4, $w12[0] # encoding: [0x78,0x38,0x61,0x19]
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test_3rf.s | 53 # CHECK: fslt.w $w12, $w5, $w6 # encoding: [0x7b,0x06,0x2b,0x1a] 55 # CHECK: fsne.w $w30, $w1, $w12 # encoding: [0x7a,0xcc,0x0f,0x9c] 58 # CHECK: fsor.d $w12, $w24, $w11 # encoding: [0x7a,0x6b,0xc3,0x1c] 76 # CHECK: maddr_q.w $w29, $w12, $w16 # encoding: [0x7b,0x70,0x67,0x5c] 79 # CHECK: msubr_q.h $w12, $w21, $w11 # encoding: [0x7b,0x8b,0xab,0x1c] 136 fslt.w $w12, $w5, $w6 138 fsne.w $w30, $w1, $w12 141 fsor.d $w12, $w24, $w11 159 maddr_q.w $w29, $w12, $w16 162 msubr_q.h $w12, $w21, $w1 [all...] |
test_mi10.s | 17 # CHECK: ld.w $w12, 1024($13) # encoding: [0x79,0x00,0x6b,0x22] 44 ld.w $w12, 1024($13)
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/system/core/libpixelflinger/arch-arm64/ |
col32cb16blend.S | 57 and w12, w9, w1, lsr #8 // extract green 60 lsl w12, w12, #6 // prescale green 72 madd w7, w7, w5, w12 // dest green * alpha + src green
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t32cb16blend.S | 155 // w12: scratch 169 pixel w3, w4, w12, 0 170 strh w12, [x0], #2 187 pixel w3, w4, w12, 0 188 pixel w3, w5, w12, 1 189 str w12, [x0, #-4] 200 pixel w3, w4, w12, 0 201 pixel w3, w5, w12, 1 202 str w12, [x0, #-4]
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/toolchain/binutils/binutils-2.25/ld/testsuite/ld-aarch64/ |
emit-relocs-279.d | 13 +10018: 3619194c tbz w12, #3, 12340 <target2>
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
msa.s | 10 slli.b $w12,$w13,0 24 srai.h $w12,$w13,0 38 srli.w $w12,$w13,0 52 bclri.d $w12,$w13,0 66 bneg.b $w12,$w13,$w14 79 binsl.h $w11,$w12,$w13 92 binsr.w $w10,$w11,$w12 106 addvi.b $w12,$w13,0 120 subvi.h $w12,$w13,0 134 maxi_s.w $w12,$w13,-1 [all...] |
msa-relax.s | 18 bz.w $w12, foo
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micromips@msa.d | 13 [0-9a-f]+ <[^>]*> 5870 6b12 slli\.b \$w12,\$w13,0x0 27 [0-9a-f]+ <[^>]*> 58e0 6b12 srai\.h \$w12,\$w13,0x0 41 [0-9a-f]+ <[^>]*> 5940 6b12 srli\.w \$w12,\$w13,0x0 55 [0-9a-f]+ <[^>]*> 5980 6b12 bclri\.d \$w12,\$w13,0x0 69 [0-9a-f]+ <[^>]*> 5a8e 6b1a bneg\.b \$w12,\$w13,\$w14 82 [0-9a-f]+ <[^>]*> 5b2d 62da binsl\.h \$w11,\$w12,\$w13 95 [0-9a-f]+ <[^>]*> 5bcc 5a9a binsr\.w \$w10,\$w11,\$w12 109 [0-9a-f]+ <[^>]*> 5800 6b29 addvi\.b \$w12,\$w13,0 123 [0-9a-f]+ <[^>]*> 58a0 6b29 subvi\.h \$w12,\$w13,0 137 [0-9a-f]+ <[^>]*> 5950 6b29 maxi_s\.w \$w12,\$w13,-1 [all...] |
mipsr6@msa.d | 13 [0-9a-f]+ <[^>]*> 78706b09 slli\.b \$w12,\$w13,0x0 27 [0-9a-f]+ <[^>]*> 78e06b09 srai\.h \$w12,\$w13,0x0 41 [0-9a-f]+ <[^>]*> 79406b09 srli\.w \$w12,\$w13,0x0 55 [0-9a-f]+ <[^>]*> 79806b09 bclri\.d \$w12,\$w13,0x0 69 [0-9a-f]+ <[^>]*> 7a8e6b0d bneg\.b \$w12,\$w13,\$w14 82 [0-9a-f]+ <[^>]*> 7b2d62cd binsl\.h \$w11,\$w12,\$w13 95 [0-9a-f]+ <[^>]*> 7bcc5a8d binsr\.w \$w10,\$w11,\$w12 109 [0-9a-f]+ <[^>]*> 78006b06 addvi\.b \$w12,\$w13,0 123 [0-9a-f]+ <[^>]*> 78a06b06 subvi\.h \$w12,\$w13,0 137 [0-9a-f]+ <[^>]*> 79506b06 maxi_s\.w \$w12,\$w13,-1 [all...] |
msa.d | 12 [0-9a-f]+ <[^>]*> 78706b09 slli\.b \$w12,\$w13,0x0 26 [0-9a-f]+ <[^>]*> 78e06b09 srai\.h \$w12,\$w13,0x0 40 [0-9a-f]+ <[^>]*> 79406b09 srli\.w \$w12,\$w13,0x0 54 [0-9a-f]+ <[^>]*> 79806b09 bclri\.d \$w12,\$w13,0x0 68 [0-9a-f]+ <[^>]*> 7a8e6b0d bneg\.b \$w12,\$w13,\$w14 81 [0-9a-f]+ <[^>]*> 7b2d62cd binsl\.h \$w11,\$w12,\$w13 94 [0-9a-f]+ <[^>]*> 7bcc5a8d binsr\.w \$w10,\$w11,\$w12 108 [0-9a-f]+ <[^>]*> 78006b06 addvi\.b \$w12,\$w13,0 122 [0-9a-f]+ <[^>]*> 78a06b06 subvi\.h \$w12,\$w13,0 136 [0-9a-f]+ <[^>]*> 79506b06 maxi_s\.w \$w12,\$w13,-1 [all...] |
/external/libhevc/common/arm64/ |
ihevc_sao_edge_offset_class0.s | 89 LDRB w12,[x11] //pu1_src_top[wd - 1] 97 STRB w12,[x4] //*pu1_src_top_left = pu1_src_top[wd - 1] 125 LDRB w12,[x7] //pu1_avail[0] 126 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0) 131 mov v3.b[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0) 136 LDRB w12,[x7,#1] //pu1_avail[1] 137 mov v3.b[15], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15) 273 LDRB w12,[x7] //pu1_avail[0] 274 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0) 279 mov v3.b[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0 [all...] |
ihevc_sao_edge_offset_class0_chroma.s | 102 LDRH w12,[x20] //pu1_src_top[wd - 1] 106 STRH w12,[x4] //*pu1_src_top_left = pu1_src_top[wd - 1] 143 LDRB w12,[x7] //pu1_avail[0] 144 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0) 145 mov v3.b[1], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 1) 150 mov v3.h[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0) 155 LDRB w12,[x7,#1] //pu1_avail[1] 156 mov v3.b[14], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 14) 157 mov v3.b[15], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15) 330 LDRB w12,[x7] //pu1_avail[0 [all...] |
ihevc_intra_pred_luma_vert.s | 182 ldrb w12, [x6] //src[2nt+1] 183 sxtw x12,w12 188 dup v24.16b,w12 //src[2nt+1] 189 dup v30.8h,w12 322 ldrb w12, [x6] //src[2nt+1] 323 sxtw x12,w12 328 dup v24.8b,w12 //src[2nt+1] 329 dup v30.8h,w12
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/external/boringssl/linux-aarch64/crypto/sha/ |
sha1-armv8.S | 151 add w20,w20,w12 // future e+=X[i] 235 eor w4,w4,w12 310 eor w10,w10,w12 334 eor w12,w12,w14 338 eor w12,w12,w4 342 eor w12,w12,w9 345 ror w12,w12,#3 [all...] |
sha256-armv8.S | 192 eor w12,w26,w26,ror#14 198 eor w16,w16,w12,ror#11 // Sigma1(e) 199 ror w12,w22,#2 206 eor w17,w12,w17,ror#13 // Sigma0(a) 213 ldp w11,w12,[x1],#2*4 260 rev w12,w12 // 9 269 add w26,w26,w12 // h+=X[i] 439 add w3,w3,w12 479 str w12,[sp,#4 [all...] |
/external/llvm/test/MC/Mips/mips32r2/ |
invalid-msa.s | 15 fexupl.w $w12,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 17 fexupr.w $w29,$w12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 21 ffint_u.w $w19,$w12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 29 flog2.d $w12,$w16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 31 frcp.d $w12,$w4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 42 ftint_u.w $w12,$w29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 48 nloc.b $w12,$w30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 52 nlzc.b $w12,$w7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 57 or.v $w13,$w23,$w12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/clang/test/CXX/dcl.dcl/dcl.attr/dcl.align/ |
p6.cpp | 65 W<1,2> w12; variable
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/external/llvm/test/MC/AArch64/ |
basic-a64-diagnostics.s | 395 cmn w11, w12, lsr #-1 396 cmn w11, w12, lsr #32 412 // CHECK-ERROR-NEXT: cmn w11, w12, lsr #-1 415 // CHECK-ERROR-NEXT: cmn w11, w12, lsr #32 444 cmp w11, w12, lsr #-1 445 cmp w11, w12, lsr #32 461 // CHECK-ERROR-NEXT: cmp w11, w12, lsr #-1 464 // CHECK-ERROR-NEXT: cmp w11, w12, lsr #32 493 neg w11, w12, lsr #-1 494 neg w11, w12, lsr #3 [all...] |