| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips64.s | 11 dclo $1, $2
|
| mips64.d | 10 0+0000 <[^>]*> 70410825 dclo at,v0
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| micromips@mips64.d | 11 [0-9a-f]+ <[^>]*> 5822 4b3c dclo at,v0
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| mipsr6@mips64.d | 11 0+0000 <[^>]*> 00400853 dclo at,v0
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| r6-64.s | 15 dclo $2,$3
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| vr5500.s | 66 dclo $3,$4
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| r6-64-n32.d | 22 0+002c <[^>]*> 00601053 dclo v0,v1
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| r6-64-n64.d | 22 0+002c <[^>]*> 00601053 dclo v0,v1
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| vr5500.d | 44 0+00090 <stuff\+0x90> dclo v1,a0
|
| set-arch.s | 299 dclo $1, $2
480 dclo $3,$4
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| set-arch.d | 205 00000314 <[^>]*> 70410825 dclo at,v0
360 00000580 <[^>]*> 70831825 dclo v1,a0
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64instrs.ll | 2 ; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s
3 ; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s
4 ; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=GPRMULDIV %s
192 ; HAS-DCLO: dclz $2, $4
202 ; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
203 ; MIPS4-NOT: dclo
205 ; HAS-DCLO: dclo $2, $4
|
| countleading.ll | 72 ; MIPS4-NOT: dclo
85 ; MIPS64-GT-R1: dclo $2, $4
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips64.s | 8 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64.s | 11 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64r2.s | 10 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64.s | 10 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64r2.s | 10 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/valgrind/none/tests/mips64/ |
| arithmetic_instruction.c | 8 DADDIU, DADDU, DCLO, DCLZ,
121 case DCLO:
123 TEST3("dclo $t0, $t1", reg_val1[i], t0, t1);
124 TEST3("dclo $v0, $v1", reg_val2[i], v0, v1);
|
| /external/llvm/lib/Target/Mips/ |
| Mips64r6InstrInfo.td | 15 // Reencoded: dclo, dclz
61 class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd>;
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2-el.txt | 87 0x25 0x90 0xd2 0x70 # CHECK: dclo $18, $6
266 0x25 0x48 0x09 0x73 # CHECK: dclo $9, $24
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 76 dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 76 dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 76 dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 76 dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25]
|
