| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 198 unsigned SubReg = *SubRegs;
199 MachineInstr *Def = PhysRegDef[SubReg];
204 LastDefReg = SubReg;
252 unsigned SubReg = *SubRegs;
253 if (Processed.count(SubReg))
255 if (PartDefRegs.count(SubReg))
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
262 PhysRegDef[SubReg] = LastPartialDef;
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
291 unsigned SubReg = *SubRegs
[all...] |
| ExpandPostRAPseudos.cpp | 100 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
104 DEBUG(dbgs() << "subreg: replaced by: " << *MI);
117 DEBUG(dbgs() << "subreg: replace by: " << *MI);
120 DEBUG(dbgs() << "subreg: eliminated!");
129 DEBUG(dbgs() << "subreg: " << *CopyMI);
|
| PeepholeOptimizer.cpp | 160 bool findNextSource(unsigned Reg, unsigned SubReg,
225 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) {
226 addSource(Reg, SubReg);
256 assert(Idx < getNumSources() && "SubReg source out of index");
257 return RegSrcs[Idx].SubReg;
406 /// result, then replace all reachable uses of the source with the subreg of the
607 /// for the value defined by \p Reg and \p SubReg.
614 /// share the same register file as \p Reg and \p SubReg. The client should
617 bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg,
628 TargetInstrInfo::RegSubRegPair CurSrcPair(Reg, SubReg);
[all...] |
| LiveRangeCalc.cpp | 65 unsigned SubReg = MO.getSubReg();
66 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
67 LaneBitmask Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
159 unsigned SubReg = MO.getSubReg();
160 if (SubReg != 0) {
161 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg);
|
| MachineInstrBundle.cpp | 187 unsigned SubReg = *SubRegs;
188 if (LocalDefSet.insert(SubReg).second)
189 LocalDefs.push_back(SubReg);
|
| VirtRegMap.cpp | 316 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
378 unsigned SubReg = MO.getSubReg();
379 if (SubReg != 0) {
414 PhysReg = TRI->getSubReg(PhysReg, SubReg);
415 assert(PhysReg && "Invalid SubReg for physical register");
|
| LiveIntervalAnalysis.cpp | 66 "enable-subreg-liveness", cl::Hidden, cl::init(true),
206 && "Separated components should only occur for unused subreg defs");
543 unsigned SubReg = MO.getSubReg();
544 if (SubReg != 0) {
545 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
[all...] |
| LiveRangeEdit.cpp | 180 // FIXME: Targets don't know how to fold subreg uses.
228 unsigned SubReg = MO.getSubReg();
229 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
|
| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
39 assert(SubReg && SubReg < getNumRegs() && "This is not a register");
44 if (*Subs == SubReg)
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.td | 36 class GP8<GPR SubReg, string n> : PPCReg<n> {
37 let HWEncoding = SubReg.HWEncoding;
38 let SubRegs = [SubReg];
53 class QFPR<FPR SubReg, string n> : PPCReg<n> {
54 let HWEncoding = SubReg.HWEncoding;
55 let SubRegs = [SubReg];
67 class VR<VF SubReg, string n> : PPCReg<n> {
68 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
70 let SubRegs = [SubReg];
76 class VSRL<FPR SubReg, string n> : PPCReg<n>
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 78 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
79 Subreg.isValid(); ++Subreg)
80 Uses.insert(*Subreg);
85 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
86 Subreg.isValid(); ++Subreg)
87 Defs.insert(*Subreg);
|
| A15SDOptimizer.cpp | 157 // Get the subreg type that is most likely to be coalesced
270 // a subreg copy of a DPR, just use that DPR.
273 // Is it a subreg copy of ssub_0?
276 DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
278 // Find the thing we're subreg copying out of - is it of the same
284 DEBUG(dbgs() << "Subreg copy is compatible - returning ");
540 // DPair has the same length as QPR and also has two DPRs as subreg.
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 112 static bool isGPR64(unsigned Reg, unsigned SubReg,
114 if (SubReg)
121 static bool isFPR64(unsigned Reg, unsigned SubReg,
125 SubReg == 0) ||
127 SubReg == AArch64::dsub);
129 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
130 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);
137 unsigned &SubReg) {
138 SubReg = 0;
146 SubReg = AArch64::dsub
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.h | 22 // Return the subreg to use for referring to the even and odd registers
|
| /external/llvm/test/CodeGen/X86/ |
| 2011-02-21-VirtRegRewriter-KillSubReg.ll | 3 ; `KillOps[*SR] == KillOp && "invalid subreg kill flags"'
|
| addr-mode-matcher.ll | 7 ; The AND should be turned into a subreg access.
|
| fast-isel-trunc-kill-subreg.ll | 7 ; method was extracing a subreg and killing the source register. The kill flag was
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 72 /// MO_Register has no subReg.
347 void setSubReg(unsigned subReg) {
349 SubReg_TargetFlags = subReg;
350 assert(SubReg_TargetFlags == subReg && "SubReg out of range");
354 /// subregister Reg:SubReg. Take any existing SubReg index into account,
355 /// using TargetRegisterInfo to compose the subreg indices if necessary.
361 /// Reg, taking any existing SubReg into account. For instance,
601 unsigned SubReg = 0
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600OptimizeVectorRegisters.cpp | 12 /// common data and/or have enough undef subreg using swizzle abilities.
192 unsigned SubReg = (*It).first;
199 .addReg(SubReg)
201 UpdatedRegToChan[SubReg] = Chan;
|
| SIRegisterInfo.cpp | 239 unsigned SubReg = NumSubRegs > 1 ?
244 .addReg(SubReg, getDefRegState(IsLoad))
280 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
293 .addReg(SubReg)
313 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
325 SubReg)
|
| SILowerControlFlow.cpp | 409 unsigned SubReg = TRI->getSubReg(VecReg, AMDGPU::sub0);
410 if (!SubReg)
411 SubReg = VecReg;
413 const TargetRegisterClass *RC = TRI->getPhysRegClass(SubReg);
414 int RegIdx = TRI->getHWRegIndex(SubReg) + Offset;
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 246 const char *const *SubRegIndexNames; // Names of subreg indexes.
495 // subreg index DefSubReg, reading from another source with class SrcRC and
528 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
533 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
[all...] |
| TargetInstrInfo.h | 165 /// expected the pre-extension value is available as a subreg of the result
263 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
344 /// Used to give some type checking when modeling Reg:SubReg.
347 unsigned SubReg;
348 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
349 : Reg(Reg), SubReg(SubReg) {}
356 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
358 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
364 /// the list is modeled as <Reg:SubReg, SubIdx>
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| rtl.h | 277 1 in a SUBREG used for SUBREG_PROMOTED_UNSIGNED_P.
292 1 in a SUBREG used for SUBREG_PROMOTED_UNSIGNED_P.
301 1 in a SUBREG expression if was generated from a variable with a
[all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| ArrayBoundCheckerV2.cpp | 266 if (const SubRegion *subReg = dyn_cast<SubRegion>(region)) {
269 return RegionRawOffsetV2(subReg, offset);
|
