/external/llvm/lib/Target/Mips/ |
MipsRegisterInfo.cpp | 86 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); 89 if (Subtarget.hasMips64()) 90 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList 93 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList 97 if (Subtarget.isSingleFloat()) 100 if (Subtarget.isABI_N64()) 103 if (Subtarget.isABI_N32()) 106 if (Subtarget.isFP64bit()) 109 if (Subtarget.isFPXX()) 118 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>() [all...] |
MipsTargetMachine.h | 34 MipsSubtarget *Subtarget; 50 if (Subtarget) 51 return Subtarget; 57 /// \brief Reset the subtarget for the Mips target.
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/external/clang/test/CodeGen/ |
target-builtin-error-2.c | 7 // the subtarget feature won't be available.
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/external/llvm/lib/Target/BPF/ |
BPFTargetMachine.h | 23 BPFSubtarget Subtarget; 30 const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; } 32 return &Subtarget;
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CMakeLists.txt | 10 tablegen(LLVM BPFGenSubtargetInfo.inc -gen-subtarget)
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BPFSubtarget.cpp | 1 //===-- BPFSubtarget.cpp - BPF Subtarget Information ----------------------===// 20 #define DEBUG_TYPE "bpf-subtarget"
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/external/llvm/lib/Target/SystemZ/ |
SystemZTargetMachine.h | 27 SystemZSubtarget Subtarget; 36 const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; } 38 return &Subtarget;
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/external/llvm/lib/Target/XCore/ |
XCoreTargetMachine.h | 24 XCoreSubtarget Subtarget; 32 const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; } 34 return &Subtarget;
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CMakeLists.txt | 9 tablegen(LLVM XCoreGenSubtargetInfo.inc -gen-subtarget)
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/external/llvm/lib/Target/MSP430/ |
CMakeLists.txt | 8 tablegen(LLVM MSP430GenSubtargetInfo.inc -gen-subtarget)
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MSP430Subtarget.cpp | 1 //===-- MSP430Subtarget.cpp - MSP430 Subtarget Information ----------------===// 20 #define DEBUG_TYPE "msp430-subtarget"
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MSP430TargetMachine.h | 28 MSP430Subtarget Subtarget; 38 return &Subtarget;
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/external/v8/build/android/ |
write_ordered_libraries.gypi | 22 'action_name': 'ordered_libraries_<(_target_name)<(subtarget)', 26 'subtarget%': '',
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/external/icu/icu4c/source/samples/ |
Makefile.in | 72 subtarget=`echo $@ | sed s/-samples-recursive//`; \ 74 echo "$(MAKE)[$(MAKELEVEL)]: Making \`$$subtarget' in \`$$subdir'"; \ 77 local_target="$$subtarget-local"; \ 79 local_target="$$subtarget"; \ 84 $(MAKE) "$$subtarget-local" || exit; \
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/external/mesa3d/src/gallium/drivers/radeon/ |
AMDGPUTargetMachine.cpp | 49 Subtarget(TT, CPU, FS), 50 DataLayout(Subtarget.getDataLayout()), 52 Subtarget.device()->getStackAlignment(), 0), 54 InstrItins(&Subtarget.getInstrItineraryData()), 59 if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
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/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); 105 if (Subtarget.hasVSX()) 107 if (Subtarget.hasAltivec()) 112 if (Subtarget.isDarwinABI()) 114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList 116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList 123 ? (Subtarget.hasAltivec() 127 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList 134 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 136 if (Subtarget.hasVSX() [all...] |
/external/llvm/lib/Target/X86/ |
X86SelectionDAGInfo.cpp | 52 const X86Subtarget &Subtarget = 70 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) { 75 V->isNullValue() ? Subtarget.getBZeroEntry() : nullptr) { 125 if (Subtarget.is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned 154 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, 157 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, 202 // within a subtarget-specific limit. 204 const X86Subtarget &Subtarget = 209 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) 240 AVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32 [all...] |
/external/llvm/lib/Target/ARM/ |
ARMSubtarget.h | 1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===// 119 /// NoARM - True if subtarget does not support ARM mode execution. 134 /// HasFP16 - True if subtarget supports half-precision FP conversions 137 /// HasFullFP16 - True if subtarget supports half-precision FP operations 140 /// HasD16 - True if subtarget is limited to 16 double precision 144 /// HasHardwareDivide - True if subtarget supports [su]div 147 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode 150 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack 154 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier 175 /// HasMPExtension - True if the subtarget supports Multiprocessin [all...] |
/external/llvm/lib/Target/WebAssembly/ |
WebAssemblySubtarget.h | 1 //=- WebAssemblySubtarget.h - Define Subtarget for the WebAssembly -*- C++ -*-// 46 /// can use initializer lists for subtarget initialization. 78 /// Parses features string setting specified subtarget options. Definition of
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WebAssemblySubtarget.cpp | 1 //===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===// 22 #define DEBUG_TYPE "wasm-subtarget"
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/external/llvm/utils/ |
schedcover.py | 3 # This creates a CSV file from the output of the debug output of subtarget: 4 # llvm-tblgen --gen-subtarget --debug-only=subtarget-emitter
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/external/llvm/lib/Target/NVPTX/ |
CMakeLists.txt | 8 tablegen(LLVM NVPTXGenSubtargetInfo.inc -gen-subtarget)
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/external/llvm/lib/Target/Sparc/ |
CMakeLists.txt | 10 tablegen(LLVM SparcGenSubtargetInfo.inc -gen-subtarget)
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SparcRegisterInfo.cpp | 57 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); 68 if (!Subtarget.is64Bit()) 83 if (ReserveAppRegisters || !Subtarget.is64Bit()) 91 if (!Subtarget.isV9()) { 104 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); 105 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; 174 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); 183 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { 185 const TargetInstrInfo &TII = *Subtarget.getInstrInfo() [all...] |
/external/llvm/test/CodeGen/ARM/ |
minsize-litpools.ll | 4 ; CodeGen should be able to set and reset the MinSize subtarget-feature, and
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