| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| x86-64-bmi.s | 13 andn %eax,%ebx,%esi
14 andn (%rcx),%ebx,%esi
15 andn %r9d,%r15d,%r10d
16 andn (%rcx),%r15d,%r10d
39 andn %rax,%rbx,%rsi
40 andn (%rcx),%rbx,%rsi
41 andn %r9,%r15,%r10
42 andn (%rcx),%r15,%r10
77 andn esi,ebx,eax
78 andn esi,ebx,DWORD PTR [rcx
[all...] |
| bmi.s | 12 andn %eax,%ebx,%esi
13 andn (%ecx),%ebx,%esi
37 andn esi,ebx,eax
38 andn esi,ebx,DWORD PTR [ecx]
39 andn esi,ebx,[ecx]
|
| inval-16.s | 6 andn (%eax), %ecx, %ecx
|
| bmi-intel.d | 14 [ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn esi,ebx,eax
15 [ ]*[a-f0-9]+: c4 e2 60 f2 31 andn esi,ebx,DWORD PTR \[ecx\]
29 [ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn esi,ebx,eax
30 [ ]*[a-f0-9]+: c4 e2 60 f2 31 andn esi,ebx,DWORD PTR \[ecx\]
31 [ ]*[a-f0-9]+: c4 e2 60 f2 31 andn esi,ebx,DWORD PTR \[ecx\]
|
| bmi.d | 13 [ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
14 [ ]*[a-f0-9]+: c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
28 [ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
29 [ ]*[a-f0-9]+: c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
30 [ ]*[a-f0-9]+: c4 e2 60 f2 31 andn \(%ecx\),%ebx,%esi
|
| x86-64-bmi-intel.d | 15 [ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn esi,ebx,eax
16 [ ]*[a-f0-9]+: c4 e2 60 f2 31 andn esi,ebx,DWORD PTR \[rcx\]
17 [ ]*[a-f0-9]+: c4 42 00 f2 d1 andn r10d,r15d,r9d
18 [ ]*[a-f0-9]+: c4 62 00 f2 11 andn r10d,r15d,DWORD PTR \[rcx\]
35 [ ]*[a-f0-9]+: c4 e2 e0 f2 f0 andn rsi,rbx,rax
36 [ ]*[a-f0-9]+: c4 e2 e0 f2 31 andn rsi,rbx,QWORD PTR \[rcx\]
37 [ ]*[a-f0-9]+: c4 42 80 f2 d1 andn r10,r15,r9
38 [ ]*[a-f0-9]+: c4 62 80 f2 11 andn r10,r15,QWORD PTR \[rcx\]
63 [ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn esi,ebx,eax
64 [ ]*[a-f0-9]+: c4 e2 60 f2 31 andn esi,ebx,DWORD PTR \[rcx\
[all...] |
| x86-64-bmi.d | 14 [ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
15 [ ]*[a-f0-9]+: c4 e2 60 f2 31 andn \(%rcx\),%ebx,%esi
16 [ ]*[a-f0-9]+: c4 42 00 f2 d1 andn %r9d,%r15d,%r10d
17 [ ]*[a-f0-9]+: c4 62 00 f2 11 andn \(%rcx\),%r15d,%r10d
34 [ ]*[a-f0-9]+: c4 e2 e0 f2 f0 andn %rax,%rbx,%rsi
35 [ ]*[a-f0-9]+: c4 e2 e0 f2 31 andn \(%rcx\),%rbx,%rsi
36 [ ]*[a-f0-9]+: c4 42 80 f2 d1 andn %r9,%r15,%r10
37 [ ]*[a-f0-9]+: c4 62 80 f2 11 andn \(%rcx\),%r15,%r10
62 [ ]*[a-f0-9]+: c4 e2 60 f2 f0 andn %eax,%ebx,%esi
63 [ ]*[a-f0-9]+: c4 e2 60 f2 31 andn \(%rcx\),%ebx,%es
[all...] |
| inval-16.l | 17 [ ]*6[ ]+andn \(%eax\), %ecx, %ecx
|
| /external/llvm/test/CodeGen/SPARC/ |
| stack-align.ll | 8 ;; andn), that the local var is accessed via stack pointer (to %o0), and that
12 ;; CHECK: andn %sp, 63, %sp
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mmix/ |
| reg3-op.s | 24 ANDN $232,$133,0
|
| reg3-op-r.d | 28 4c: cbe88500 andn \$232,\$133,0
|
| reg3-op.d | 26 4c: cbe88500 andn \$232,\$133,0
|
| reg3-op.l | 27 24 004c CBE88500 ANDN \$232,\$133,0
|
| /external/llvm/test/CodeGen/Hexagon/intrinsics/ |
| cr.ll | 81 declare i32 @llvm.hexagon.C2.andn(i32, i32)
83 %z = call i32@llvm.hexagon.C2.andn(i32 %a, i32 %b)
95 declare i32 @llvm.hexagon.C4.and.andn(i32, i32, i32)
97 %z = call i32@llvm.hexagon.C4.and.andn(i32 %a, i32 %b, i32 %c)
116 declare i32 @llvm.hexagon.C4.or.andn(i32, i32, i32)
118 %z = call i32@llvm.hexagon.C4.or.andn(i32 %a, i32 %b, i32 %c)
|
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/ppc64/ |
| anames.go | 31 "ANDN",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/ppc64/ |
| anames.go | 31 "ANDN",
|
| /external/llvm/test/CodeGen/X86/ |
| peep-test-4.ll | 137 ; CHECK-LABEL: andn:
142 define void @andn(i32 %x, i32 %y) nounwind {
144 %andn = and i32 %y, %not
145 %cmp = icmp eq i32 %andn, 0
149 tail call void @foo(i32 %andn)
|
| /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/internal/obj/ppc64/ |
| anames.go | 34 "ANDN",
|
| /prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/internal/obj/ppc64/ |
| anames.go | 34 "ANDN",
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic4x/ |
| allopcodes.S | 38 AU_CLASS( andn, TEST_C3X )
39 T_CLASS( andn, TEST_C3X )
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mcore/ |
| allinsn.s | 17 test andn "r9, r10"
|
| /external/clang/test/CodeGen/ |
| avx512vldq-builtins.c | 46 // CHECK: @llvm.x86.avx512.mask.andn.pd.256
52 // CHECK: @llvm.x86.avx512.mask.andn.pd.256
58 // CHECK: @llvm.x86.avx512.mask.andn.pd.128
64 // CHECK: @llvm.x86.avx512.mask.andn.pd.128
70 // CHECK: @llvm.x86.avx512.mask.andn.ps.256
76 // CHECK: @llvm.x86.avx512.mask.andn.ps.256
82 // CHECK: @llvm.x86.avx512.mask.andn.ps.128
88 // CHECK: @llvm.x86.avx512.mask.andn.ps.128
|
| avx512dq-builtins.c | 136 // CHECK: @llvm.x86.avx512.mask.andn.pd.512
142 // CHECK: @llvm.x86.avx512.mask.andn.pd.512
148 // CHECK: @llvm.x86.avx512.mask.andn.pd.512
154 // CHECK: @llvm.x86.avx512.mask.andn.ps.512
160 // CHECK: @llvm.x86.avx512.mask.andn.ps.512
166 // CHECK: @llvm.x86.avx512.mask.andn.ps.512
|
| /external/llvm/test/MC/Sparc/ |
| sparc-alu-instructions.s | 27 ! CHECK: andn %g1, %g2, %g3 ! encoding: [0x86,0x28,0x40,0x02]
28 andn %g1, %g2, %g3
|
| /external/bison/lib/ |
| bbitset.h | 136 void (*andn) (bitset, bitset, bitset); member in struct:bitset_vtable
234 #define BITSET_ANDN_(DST, SRC1, SRC2) (SRC1)->b.vtable->andn (DST, SRC1, SRC2)
|
