| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips64.s | 12 dclz $3, $4
|
| mips64.d | 11 0+0004 <[^>]*> 70831824 dclz v1,a0
|
| micromips@mips64.d | 12 [0-9a-f]+ <[^>]*> 5864 5b3c dclz v1,a0
|
| mipsr6@mips64.d | 12 0+0004 <[^>]*> 00801852 dclz v1,a0
|
| r6-64.s | 14 dclz $2,$3
|
| vr5500.s | 68 dclz $3,$4
|
| r6-64-n32.d | 21 0+0028 <[^>]*> 00601052 dclz v0,v1
|
| r6-64-n64.d | 21 0+0028 <[^>]*> 00601052 dclz v0,v1
|
| vr5500.d | 46 0+00098 <stuff\+0x98> dclz v1,a0
|
| set-arch.s | 300 dclz $3, $4
482 dclz $3,$4
|
| set-arch.d | 206 00000318 <[^>]*> 70831824 dclz v1,a0
362 00000588 <[^>]*> 70831824 dclz v1,a0
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips64.s | 9 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64instrs.ll | 189 ; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
190 ; MIPS4-NOT: dclz
192 ; HAS-DCLO: dclz $2, $4
|
| countleading.ll | 49 ; MIPS4-NOT: dclz
60 ; MIPS64-GT-R1: dclz $2, $4
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64.s | 12 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64r2.s | 11 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64.s | 11 dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64r2.s | 11 dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/valgrind/none/tests/mips64/ |
| arithmetic_instruction.c | 8 DADDIU, DADDU, DCLO, DCLZ,
127 case DCLZ:
129 TEST3("dclz $t0, $t1", reg_val1[i], t0, t1);
130 TEST3("dclz $v0, $v1", reg_val2[i], v0, v1);
|
| /external/llvm/lib/Target/Mips/ |
| Mips64r6InstrInfo.td | 15 // Reencoded: dclo, dclz
62 class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>;
|
| /external/pcre/dist/sljit/ |
| sljitNativeMIPS_64.c | 222 FAIL_IF(push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(src2) | TA(EQUAL_FLAG) | DA(EQUAL_FLAG), EQUAL_FLAG));
224 FAIL_IF(push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(src2) | T(dst) | D(dst), DR(dst)));
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2-el.txt | 88 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
267 0x24 0xd0 0x3a 0x71 # CHECK: dclz $26, $9
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
