| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| float.s | 58 fdivr
59 fdivr %st(3)
60 fdivr %st(3),%st
61 fdivr %st,%st(3)
|
| compat.s | 15 fdivr %st,%st(3)
|
| float.l | 70 58 006e DEF9 [ ]*fdivr
72 59 0070 D8FB [ ]*fdivr %st\(3\)
73 60 0072 D8FB [ ]*fdivr %st\(3\),%st
74 61 0074 DCFB [ ]*fdivr %st,%st\(3\)
|
| compat-intel.d | 19 [ ]*[a-f0-9]+: dc f3 fdivr st\(3\),st
|
| compat.d | 22 [ ]*[a-f0-9]+: dc fb fdivr %st,%st\(3\)
|
| intel.s | 654 fdivr label
655 fdivr st(3) label
656 fdivr st,st(3) label
657 fdivr st(3),st label
658 fdivr DWORD PTR [ebx] label
659 fdivr QWORD PTR [ebx] label
|
| general.s | 144 fdivr
|
| general.l | 215 144 015e DEF9 fdivr
|
| /external/llvm/test/MC/X86/ |
| intel-syntax-2.s | 30 fdivr label
|
| intel-syntax.s | 550 fdivr label
570 // CHECK: fdivr %st(1)
576 fdivr ST(0), ST(1) label
582 // CHECK: fdivr %st(0), %st(1)
589 fdivr ST(1), ST(0) label
596 // CHECK: fdivr %st(1)
602 fdivr ST(1) label
|
| x86-64.s | 1345 // CHECK: fdivr %st(1)
1351 fdivr %st(1), %st(0) label
1358 // CHECK: fdivr %st(0), %st(1)
1364 fdivr %st(0), %st(1) label
1371 // CHECK: fdivr %st(1)
1377 fdivr %st(1) label
|
| x86-16.s | 235 // CHECK: fdivr %st(0)
237 fdivr %st(0), %st
|
| x86-32.s | 341 // CHECK: fdivr %st(0)
343 fdivr %st(0), %st
|
| /external/llvm/test/MC/Disassembler/X86/ |
| fp-stack.txt | 172 # CHECK: fdivr %st(0)
175 # CHECK: fdivr %st(1)
178 # CHECK: fdivr %st(2)
181 # CHECK: fdivr %st(3)
184 # CHECK: fdivr %st(4)
187 # CHECK: fdivr %st(5)
190 # CHECK: fdivr %st(6)
193 # CHECK: fdivr %st(7)
697 # CHECK: fdivr %st(0), %st(0)
700 # CHECK: fdivr %st(0), %st(1
[all...] |
| /external/valgrind/none/tests/amd64/ |
| insn_fpu.def | 153 fdivr st0.ps[1234.5678] st2.ps[8765.4321] => st2.ps[7.10000058320005]
154 fdivr st0.ps[-1234.5678] st2.ps[8765.4321] => st2.ps[-7.10000058320005]
155 fdivr st0.ps[1234.5678] st2.ps[-8765.4321] => st2.ps[-7.10000058320005]
156 fdivr st0.ps[-1234.5678] st2.ps[-8765.4321] => st2.ps[7.10000058320005]
157 fdivr st0.pd[1234567.7654321] st2.pd[7654321.1234567] => st2.pd[6.20000079200001]
158 fdivr st0.pd[-1234567.7654321] st2.pd[7654321.1234567] => st2.pd[-6.20000079200001]
159 fdivr st0.pd[1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[-6.20000079200001]
160 fdivr st0.pd[-1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[6.20000079200001]
161 fdivr st2.ps[1234.5678] st0.ps[8765.4321] => st0.ps[0.140845058853402]
162 fdivr st2.ps[-1234.5678] st0.ps[8765.4321] => st0.ps[-0.140845058853402
[all...] |
| /external/valgrind/none/tests/x86/ |
| insn_fpu.def | 153 fdivr st0.ps[1234.5678] st2.ps[8765.4321] => st2.ps[7.10000058320005]
154 fdivr st0.ps[-1234.5678] st2.ps[8765.4321] => st2.ps[-7.10000058320005]
155 fdivr st0.ps[1234.5678] st2.ps[-8765.4321] => st2.ps[-7.10000058320005]
156 fdivr st0.ps[-1234.5678] st2.ps[-8765.4321] => st2.ps[7.10000058320005]
157 fdivr st0.pd[1234567.7654321] st2.pd[7654321.1234567] => st2.pd[6.20000079200001]
158 fdivr st0.pd[-1234567.7654321] st2.pd[7654321.1234567] => st2.pd[-6.20000079200001]
159 fdivr st0.pd[1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[-6.20000079200001]
160 fdivr st0.pd[-1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[6.20000079200001]
161 fdivr st2.ps[1234.5678] st0.ps[8765.4321] => st0.ps[0.140845058853402]
162 fdivr st2.ps[-1234.5678] st0.ps[8765.4321] => st0.ps[-0.140845058853402
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/rsc.io/x86/x86asm/ |
| gnu.go | 22 case FDIV, FDIVR, FSUB, FSUBR, FDIVP, FDIVRP, FSUBP, FSUBRP:
23 // DC E0, DC F0: libopcodes swaps FSUBR/FSUB and FDIVR/FDIV, at least
33 inst.Op = FDIVR
34 case FDIVR:
914 case FADD, FCOM, FCOMP, FDIV, FDIVR, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FIST, FISTP, FISTTP, FISUB, FISUBR, FLD, FMUL, FST, FSTP, FSUB, FSUBR:
|
| intel.go | 295 case FLD, FXCH, FCOM, FCOMP, FIADD, FIMUL, FICOM, FICOMP, FISUBR, FIDIV, FUCOM, FUCOMP, FILD, FBLD, FADD, FMUL, FSUB, FSUBR, FISUB, FDIV, FDIVR, FIDIVR:
|
| /prebuilts/go/linux-x86/src/cmd/internal/rsc.io/x86/x86asm/ |
| gnu.go | 22 case FDIV, FDIVR, FSUB, FSUBR, FDIVP, FDIVRP, FSUBP, FSUBRP:
23 // DC E0, DC F0: libopcodes swaps FSUBR/FSUB and FDIVR/FDIV, at least
33 inst.Op = FDIVR
34 case FDIVR:
914 case FADD, FCOM, FCOMP, FDIV, FDIVR, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FIST, FISTP, FISTTP, FISUB, FISUBR, FLD, FMUL, FST, FSTP, FSUB, FSUBR:
|
| intel.go | 295 case FLD, FXCH, FCOM, FCOMP, FIADD, FIMUL, FICOM, FICOMP, FISUBR, FIDIV, FUCOM, FUCOMP, FILD, FBLD, FADD, FMUL, FSUB, FSUBR, FISUB, FDIV, FDIVR, FIDIVR:
|
| /external/google-breakpad/src/third_party/libdisasm/ |
| ia32_opcode_tables.c | [all...] |
| ia32_implicit.c | 105 /* D8, DA : FDIVR : rw ST(0) */
|
| /external/valgrind/VEX/useful/ |
| hd_fpu.c | 766 case 7: /* FDIVR single-real */
809 case 0xF8 ... 0xFF: /* FDIVR %st(?),%st(0) */
[all...] |
| /external/mesa3d/src/mesa/x86/ |
| assyntax.h | 717 #define FDIVR2(a, b) CHOICE(fdivr ARG2(a,b), fdivr ARG2(a,b), fdivr ARG2(b,a))
[all...] |
| /external/elfutils/libcpu/defs/ |
| i386 | 312 11011000,11111{freg}:fdivr {freg},%st
313 11011100,11111{freg}:fdivr %st,{freg}
314 11011{D}00,{mod}111{r_m}:fdivr{D} {mod}{r_m}
[all...] |
