| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/hppa/basic/ |
| fp_comp2.s | 19 fneg,sgl %fr5,%fr10R
20 fneg,dbl %fr5,%fr10
21 fneg,quad %fr5,%fr10
22 fneg,sgl %fr20R,%fr24L
23 fneg,dbl %fr20,%fr24
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| fneg.f64.ll | 7 %fneg = fsub double -0.000000e+00, %in
8 store double %fneg, double addrspace(1)* %out
16 %fneg = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %in
17 store <2 x double> %fneg, <2 x double> addrspace(1)* %out
32 %fneg = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %in
33 store <4 x double> %fneg, <4 x double> addrspace(1)* %out
38 ; (fneg (f64 bitcast (i64 a))) => (f64 bitcast (xor (i64 a), 0x80000000))
|
| fneg.ll | 10 %fneg = fsub float -0.000000e+00, %in
11 store float %fneg, float addrspace(1)* %out
22 %fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
23 store <2 x float> %fneg, <2 x float> addrspace(1)* %out
38 %fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
39 store <4 x float> %fneg, <4 x float> addrspace(1)* %out
44 ; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
|
| llvm.AMDGPU.clamp.ll | 40 %src.fneg = fsub float -0.0, %src
41 %clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg, float 0.0, float 1.0) nounwind readnone
53 %src.fneg.fabs = fsub float -0.0, %src.fabs
54 %clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg.fabs, float 0.0, float 1.0) nounwind readnone
|
| cvt_flr_i32_f32.ll | 52 %x.fneg = fsub float -0.000000e+00, %x
53 %floor = call float @llvm.floor.f32(float %x.fneg) #1
66 %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
67 %floor = call float @llvm.floor.f32(float %x.fabs.fneg) #1
|
| cvt_rpi_i32_f32.ll | 41 %x.fneg = fsub float -0.000000e+00, %x
42 %fadd = fadd float %x.fneg, 0.5
60 %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
61 %fadd = fadd float %x.fabs.fneg, 0.5
|
| commute_modifiers.ll | 30 %x.fneg.fabs = fsub float -0.000000e+00, %x.fabs
31 %z = fmul float 4.0, %x.fneg.fabs
44 %x.fneg = fsub float -0.000000e+00, %x
45 %z = fmul float 4.0, %x.fneg
94 %y.fneg = fsub float -0.000000e+00, %y
95 %z = fmul float %x, %y.fneg
112 %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
113 %z = fmul float %x, %y.fabs.fneg
150 %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
151 %z = fmul float %x.fabs, %y.fabs.fneg
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| fneg.ll | 1 ; RUN: llc < %s -march=ppc32 | not grep fneg
|
| /external/llvm/test/CodeGen/X86/ |
| vec_fneg.ll | 3 ; FNEG is defined as subtraction from -0.0.
14 ; This test verifies that we generate an FP subtraction because "0.0 - x" is not an fneg.
43 %fneg = fsub <2 x float> <float -0.0, float -0.0>, %bitcast
44 ret <2 x float> %fneg
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10300/ |
| am33-2.s | 780 fneg fs0
781 fneg fs26
782 fneg fs13
783 fneg fs7
784 fneg fs20
785 fneg fs14
786 fneg fs1
787 fneg fs27
788 fneg fs8
789 fneg fs
[all...] |
| /dalvik/dx/tests/102-verify-nonwide-math/ |
| op_fneg.j | 23 fneg
|
| run | 34 oneop fneg
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-fp-contract-zero.ll | 4 ; Make sure we don't try to fold an fneg into +0.0, creating an illegal constant
|
| arm64-fcopysign.ll | 18 ; CHECK: fneg.2d v2, v2
28 ; CHECK: fneg.2d v2, v{{[0-9]+}}
|
| vector-fcopysign.ll | 38 ; CHECK-NEXT: fneg.2d v2, v2
49 ; CHECK-NEXT: fneg.2d v2, v2
126 ; CHECK-NEXT: fneg.2d v2, v2
138 ; CHECK-NEXT: fneg.2d v2, v2
155 ; CHECK-NEXT: fneg.2d v3, v3
168 ; CHECK-NEXT: fneg.2d v4, v4
|
| /external/llvm/test/CodeGen/Generic/ |
| fneg-fabs.ll | 3 define double @fneg(double %X) {
|
| /external/compiler-rt/lib/builtins/ |
| negsf2.c | 17 ARM_EABI_FNALIAS(fneg, negsf2)
|
| /external/llvm/test/CodeGen/Hexagon/ |
| opt-fneg.ll | 2 ; Optimize fneg to togglebit in V5.
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/ |
| fp.s | 29 fneg fr0
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrVFP.td | 345 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
350 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
399 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
402 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
707 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
712 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
[all...] |
| /external/valgrind/none/tests/ppc32/ |
| jm-fp.stdout.exp | [all...] |
| jm-fp.stdout.exp-BE2 | [all...] |
| /external/valgrind/none/tests/ppc64/ |
| jm-fp.stdout.exp | [all...] |
| jm-fp.stdout.exp-BE2 | [all...] |
| jm-fp.stdout.exp-LE | [all...] |
