/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
floatdp2.d | 16 20: 1e2f88e0 fnmul s0, s7, s15 25 44: 1e6f88e0 fnmul d0, d7, d15
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floatdp2.s | 29 .irp op, FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
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/external/llvm/test/CodeGen/AArch64/ |
floatdp_2source.ll | 27 ; CHECK: fnmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} 55 ; CHECK: fnmul {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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/external/llvm/test/MC/AArch64/ |
arm64-fp-encoding.s | 136 fnmul h1, h2, h3 137 fnmul s1, s2, s3 138 fnmul d1, d2, d3 140 ; FP16: fnmul h1, h2, h3 ; encoding: [0x41,0x88,0xe3,0x1e] 142 ; NO-FP16-NEXT: fnmul h1, h2, h3 143 ; CHECK: fnmul s1, s2, s3 ; encoding: [0x41,0x88,0x23,0x1e] 144 ; CHECK: fnmul d1, d2, d3 ; encoding: [0x41,0x88,0x63,0x1e]
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basic-a64-instructions.s | [all...] |
basic-a64-diagnostics.s | [all...] |
/external/llvm/test/MC/Disassembler/AArch64/ |
arm64-scalar-fp.txt | 112 # FP16: fnmul h1, h2, h3 113 # CHECK: fnmul s1, s2, s3 114 # CHECK: fnmul d1, d2, d3
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basic-a64-instructions.txt | [all...] |
/external/v8/src/arm64/ |
constants-arm64.h | [all...] |
disasm-arm64.cc | 1034 FORMAT(FNMUL, "fnmul"); [all...] |
/external/vixl/src/vixl/a64/ |
constants-a64.h | [all...] |
disasm-a64.cc | [all...] |
macro-assembler-a64.h | [all...] |
simulator-a64.h | [all...] |
assembler-a64.h | [all...] |
logic-a64.cc | 3903 LogicVRegister Simulator::fnmul(VectorFormat vform, function in class:vixl::Simulator [all...] |
simulator-a64.cc | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64SchedCyclone.td | 513 // FMUL,FMULX,FNMUL default to WriteFMul.
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/external/vixl/doc/ |
supported-instructions.md | [all...] |
/external/valgrind/none/tests/arm64/ |
fp_and_simd.c | [all...] |
/external/vixl/test/ |
test-simulator-traces-a64.h | 489 #include "traces/a64/sim-fnmul-d-trace-a64.h" 490 #include "traces/a64/sim-fnmul-s-trace-a64.h" [all...] |
test-disasm-a64.cc | [all...] |
test-simulator-a64.cc | [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
aarch64-dis-2.c | [all...] |
aarch64-tbl.h | [all...] |