| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| reg.s | 5 psrlw $2, %mm6 label
6 psrlw $2, %xmm6 label
25 psrlw mm6, 2 label
26 psrlw xmm6, 2 label
|
| x86-64-reg.s | 5 psrlw $2, %mm6 label
6 psrlw $2, %xmm10 label
25 psrlw mm6, 2 label
26 psrlw xmm2, 2 label
|
| reg-intel.d | 11 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2
12 [ ]*[a-f0-9]+: 66 0f 71 d6 02 psrlw xmm6,0x2
29 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2
30 [ ]*[a-f0-9]+: 66 0f 71 d6 02 psrlw xmm6,0x2
|
| x86-64-reg-intel.d | 11 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2
12 [ ]*[a-f0-9]+: 66 41 0f 71 d2 02 psrlw xmm10,0x2
29 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2
30 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw xmm2,0x2
|
| /external/llvm/test/CodeGen/X86/ |
| 2007-03-24-InlineAsmXConstraint.ll | 8 ; CHECK: psrlw $8, %xmm0
11 tail call void asm sideeffect "psrlw $0, %xmm0", "X,~{dirflag},~{fpsr},~{flags}"( i32 8 )
|
| 2012-02-23-mmx-inlineasm.ll | 5 ; CHECK: psrlw %mm0, %mm1
7 call void asm sideeffect "psrlw $0, %mm1", "y,~{dirflag},~{fpsr},~{flags}"(i32 8) nounwind
|
| pr16807.ll | 11 ; CHECK: psrlw
15 ; CHECK: psrlw
|
| vector-popcnt-128.ll | 60 ; SSSE3-NEXT: psrlw $4, %xmm0
76 ; SSE41-NEXT: psrlw $4, %xmm0
162 ; SSSE3-NEXT: psrlw $4, %xmm0
184 ; SSE41-NEXT: psrlw $4, %xmm0
223 ; SSE2-NEXT: psrlw $1, %xmm1
229 ; SSE2-NEXT: psrlw $2, %xmm0
233 ; SSE2-NEXT: psrlw $4, %xmm1
239 ; SSE2-NEXT: psrlw $8, %xmm0
245 ; SSE3-NEXT: psrlw $1, %xmm1
251 ; SSE3-NEXT: psrlw $2, %xmm
[all...] |
| vector-tzcnt-128.ll | 226 ; SSSE3-NEXT: psrlw $4, %xmm2
251 ; SSE41-NEXT: psrlw $4, %xmm2
381 ; SSSE3-NEXT: psrlw $4, %xmm2
406 ; SSE41-NEXT: psrlw $4, %xmm2
472 ; SSE2-NEXT: psrlw $1, %xmm0
478 ; SSE2-NEXT: psrlw $2, %xmm1
482 ; SSE2-NEXT: psrlw $4, %xmm2
488 ; SSE2-NEXT: psrlw $8, %xmm0
498 ; SSE3-NEXT: psrlw $1, %xmm0
504 ; SSE3-NEXT: psrlw $2, %xmm
[all...] |
| lower-vec-shift.ll | 16 ; SSE: psrlw
17 ; SSE-NEXT: psrlw
33 ; SSE: psrlw
34 ; SSE-NEXT: psrlw
|
| /external/mesa3d/src/mesa/x86/ |
| mmx_blend.S | 32 PSRLW ( CONST(8), MA1 ) /* t1 >> 8 ~= t1/255 */ ;\
33 TWO(PSRLW ( CONST(8), MA2 )) /* t2 >> 8 ~= t2/255 */
54 PSRLW ( CONST(8), MA1 ) /* t1 >> 8 */ ;\
57 TWO(PSRLW ( CONST(8), MA2 )) /* t2 >> 8 */ ;\
60 PSRLW ( CONST(8), MA1 ) /* sa1 | sb1 | sg1 | sr1 */ ;\
63 TWO(PSRLW ( CONST(8), MA2 )) /* sa2 | sb2 | sg2 | sr2 */
85 PSRLW ( CONST(8), MA1 ) /* t1 >> 8 */ ;\
88 TWO(PSRLW ( CONST(8), MA2 )) /* t2 >> 8 */ ;\
91 PSRLW ( CONST(8), MA1 ) /* sa1 | sb1 | sg1 | sr1 */ ;\
94 TWO(PSRLW ( CONST(8), MA2 )) /* sa2 | sb2 | sg2 | sr2 *
[all...] |
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| row_x86.asm | 28 psrlw m2, m2, 8
40 psrlw m0, m0, 8 ; UYVY odd bytes are Y
41 psrlw m1, m1, 8
74 psrlw m4, m4, 8
82 psrlw m2, m0, 8 ; odd bytes
83 psrlw m3, m1, 8
|
| scale_gcc.cc | 107 "psrlw $0x8,%%xmm0 \n"
108 "psrlw $0x8,%%xmm1 \n"
125 "psrlw $0x8,%%xmm5 \n"
133 "psrlw $0x8,%%xmm0 \n"
135 "psrlw $0x8,%%xmm1 \n"
156 "psrlw $0x8,%%xmm5 \n"
168 "psrlw $0x8,%%xmm0 \n"
170 "psrlw $0x8,%%xmm1 \n"
204 "psrlw $0x8,%%xmm0 \n"
222 "psrlw $0x8,%%xmm7 \n
[all...] |
| scale_win.cc | 111 psrlw xmm0, 8 // isolate odd pixels.
112 psrlw xmm1, 8
133 psrlw xmm5, 8
141 psrlw xmm0, 8
143 psrlw xmm1, 8
170 psrlw xmm5, 8
182 psrlw xmm0, 8
184 psrlw xmm1, 8
329 psrlw xmm0, 8
353 psrlw xmm7,
[all...] |
| /external/libjpeg-turbo/simd/ |
| jcsample-mmx.asm | 104 psrlw mm6,BYTE_BIT ; mm6={0xFF 0x00 0xFF 0x00 ..}
125 psrlw mm2,BYTE_BIT
127 psrlw mm3,BYTE_BIT
133 psrlw mm0,1
134 psrlw mm1,1
246 psrlw mm6,BYTE_BIT ; mm6={0xFF 0x00 0xFF 0x00 ..}
270 psrlw mm4,BYTE_BIT
272 psrlw mm5,BYTE_BIT
279 psrlw mm4,BYTE_BIT
281 psrlw mm5,BYTE_BI
[all...] |
| jcsample-sse2-64.asm | 101 psrlw xmm6,BYTE_BIT ; xmm6={0xFF 0x00 0xFF 0x00 ..}
131 psrlw xmm2,BYTE_BIT
133 psrlw xmm3,BYTE_BIT
139 psrlw xmm0,1
140 psrlw xmm1,1
245 psrlw xmm6,BYTE_BIT ; xmm6={0xFF 0x00 0xFF 0x00 ..}
279 psrlw xmm4,BYTE_BIT
281 psrlw xmm5,BYTE_BIT
288 psrlw xmm4,BYTE_BIT
290 psrlw xmm5,BYTE_BI
[all...] |
| jcsample-sse2.asm | 104 psrlw xmm6,BYTE_BIT ; xmm6={0xFF 0x00 0xFF 0x00 ..}
137 psrlw xmm2,BYTE_BIT
139 psrlw xmm3,BYTE_BIT
145 psrlw xmm0,1
146 psrlw xmm1,1
259 psrlw xmm6,BYTE_BIT ; xmm6={0xFF 0x00 0xFF 0x00 ..}
296 psrlw xmm4,BYTE_BIT
298 psrlw xmm5,BYTE_BIT
305 psrlw xmm4,BYTE_BIT
307 psrlw xmm5,BYTE_BI
[all...] |
| /external/libvpx/libvpx/vp9/encoder/x86/ |
| vp9_quantize_ssse3_x86_64.asm | 38 psrlw m5, 15
40 psrlw m1, 1 ; m1 = (m1 + 1) / 2
82 psrlw m8, 1
83 psrlw m13, 1
86 psrlw m0, m3, 2
88 psrlw m0, m3, 1
135 psrlw m14, 1
136 psrlw m13, 1
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vpx_scale/win32/ |
| scaleopt.c | 123 psrlw mm1, 8
184 psrlw mm1, 8
190 psrlw mm3, 8
205 psrlw mm5, 8
257 psrlw mm1, 8;
260 psrlw mm0, 8;
274 psrlw mm1, 8
290 psrlw mm1, 8;
293 psrlw mm0, 8;
304 psrlw mm1,
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/ |
| x86-64-reg-intel.d | 11 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2
12 [ ]*[a-f0-9]+: 66 41 0f 71 d2 02 psrlw xmm10,0x2
29 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw mm6,0x2
30 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw xmm2,0x2
|
| x86-64-reg.d | 11 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6
12 [ ]*[a-f0-9]+: 66 41 0f 71 d2 02 psrlw \$0x2,%xmm10
29 [ ]*[a-f0-9]+: 0f 71 d6 02 psrlw \$0x2,%mm6
30 [ ]*[a-f0-9]+: 66 0f 71 d2 02 psrlw \$0x2,%xmm2
|
| /external/libvpx/libvpx/vpx_dsp/x86/ |
| highbd_subpel_variance_impl_sse2.asm | 339 psrlw m1, 4
340 psrlw m0, 4
367 psrlw m1, 4
368 psrlw m0, 4
569 psrlw m1, 4
572 psrlw m0, 4
608 psrlw m4, 4
611 psrlw m0, 4
683 psrlw m1, 4
684 psrlw m0,
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/encoder/x86/ |
| vp9_quantize_ssse3.asm | 41 psrlw m5, 15
44 psrlw m0, 1 ; m0 = (m0 + 1) / 2
45 psrlw m1, 1 ; m1 = (m1 + 1) / 2
98 psrlw m8, 1
99 psrlw m13, 1
151 psrlw m14, 1
152 psrlw m13, 1
|
| /external/libvpx/libvpx/vp8/encoder/x86/ |
| quantize_mmx.asm | 214 psrlw mm0, 15
216 psrlw mm1, 15
237 psrlw mm0, 15
239 psrlw mm1, 15
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/encoder/x86/ |
| quantize_mmx.asm | 214 psrlw mm0, 15
216 psrlw mm1, 15
237 psrlw mm0, 15
239 psrlw mm1, 15
|
