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  /external/mesa3d/src/gallium/drivers/r600/
SConscript 11 r600 = env.ConvenienceLibrary(
12 target = 'r600',
16 env.Alias('r600', r600)
18 Export('r600')
  /external/llvm/test/CodeGen/AMDGPU/
call_fs.ll 2 ; RUN: llc < %s -march=r600 -mcpu=redwood -show-mc-encoding -o - | FileCheck --check-prefix=EG %s
3 ; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600 %s
8 ; R600: .long 257
9 ; R600: {{^}}call_fs:
10 ; R600:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89]
build_vector.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
5 ; R600: {{^}}build_vector2:
6 ; R600: MOV
7 ; R600: MOV
8 ; R600-NOT: MOV
19 ; R600: {{^}}build_vector4:
20 ; R600: MOV
21 ; R600: MOV
22 ; R600: MO
    [all...]
llvm.AMDGPU.umul24.ll 3 ; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4 ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
5 ; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
6 ; XUN: llc -march=r600 -mcpu=r770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
12 ; R600: MUL_UINT24
13 ; R600: MULLO_UINT
llvm.AMDGPU.imad24.ll 3 ; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
4 ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
5 ; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
6 ; XUN: llc -march=r600 -mcpu=r770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
15 ; R600: MULLO_INT
16 ; R600: ADD_IN
    [all...]
fdiv.ll 1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
10 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
11 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
12 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
13 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
27 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
28 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
29 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
30 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, P
    [all...]
load.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
12 ; R600: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
23 ; R600: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
24 ; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
25 ; R600: 8
36 ; R600: VTX_READ_8
37 ; R600: VTX_READ_
    [all...]
fadd.ll 1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
6 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
15 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
16 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
26 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ; R600: AD
    [all...]
wrong-transalu-pos-fix.ll 1 ; RUN: llc -march=r600 -mcpu=redwood -mtriple=r600-- < %s | FileCheck %s
9 %x.i = tail call i32 @llvm.r600.read.global.size.x() #1
10 %y.i18 = tail call i32 @llvm.r600.read.global.size.y() #1
12 %z.i17 = tail call i32 @llvm.r600.read.global.size.z() #1
14 %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
15 %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
17 %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
20 %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
21 %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #
    [all...]
annotate-kernel-features.ll 4 declare i32 @llvm.r600.read.tgid.x() #0
5 declare i32 @llvm.r600.read.tgid.y() #0
6 declare i32 @llvm.r600.read.tgid.z() #0
8 declare i32 @llvm.r600.read.tidig.x() #0
9 declare i32 @llvm.r600.read.tidig.y() #0
10 declare i32 @llvm.r600.read.tidig.z() #0
12 declare i32 @llvm.r600.read.local.size.x() #0
13 declare i32 @llvm.r600.read.local.size.y() #0
14 declare i32 @llvm.r600.read.local.size.z() #0
16 declare i32 @llvm.r600.read.global.size.x() #
    [all...]
infinite-loop-evergreen.ll 2 ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s
llvm.AMDGPU.trunc.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 %s
5 ; R600: {{^}}amdgpu_trunc:
6 ; R600: TRUNC {{\*? *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
r600-encoding.ll 1 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG %s
2 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s
4 ; The earliest R600 GPUs have a slightly different encoding than the rest of
10 ; R600: {{^}}test:
11 ; R600: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]
19 call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
23 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
llvm.rint.ll 1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
6 ; R600: RNDNE
17 ; R600: RNDNE
18 ; R600: RNDNE
30 ; R600: RNDNE
31 ; R600: RNDNE
32 ; R600: RNDNE
33 ; R600: RNDNE
47 ; R600: RNDN
    [all...]
bfi_int.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 %s
8 ; R600: {{^}}bfi_def:
9 ; R600: BFI_INT
24 ; R600: {{^}}bfi_sha256_ch:
25 ; R600: BFI_INT
39 ; R600: {{^}}bfi_sha256_ma:
40 ; R600: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W
41 ; R600: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W
rotr.ll 1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s
6 ; R600: BIT_ALIGN_INT
20 ; R600: BIT_ALIGN_INT
21 ; R600: BIT_ALIGN_INT
36 ; R600: BIT_ALIGN_INT
37 ; R600: BIT_ALIGN_INT
38 ; R600: BIT_ALIGN_INT
39 ; R600: BIT_ALIGN_INT
llvm.AMDGPU.barrier.global.ll 2 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
12 %0 = call i32 @llvm.r600.read.tidig.x()
16 %2 = call i32 @llvm.r600.read.local.size.x()
27 declare i32 @llvm.r600.read.tidig.x() #0
28 declare i32 @llvm.r600.read.local.size.x() #0
  /external/mesa3d/docs/
GL3.txt 17 Conditional rendering (GL_NV_conditional_render) DONE (i965, r300, r600, swrast)
18 Map buffer subranges (GL_ARB_map_buffer_range) DONE (i965, r300, r600, swrast)
19 Clamping controls (GL_ARB_color_buffer_float) DONE (i965, r300, r600)
20 Float textures, renderbuffers (GL_ARB_texture_float) DONE (i965, r300, r600)
21 GL_EXT_packed_float DONE (i965, r600)
22 GL_EXT_texture_shared_exponent DONE (i965, r600, swrast)
23 Float depth buffers (GL_ARB_depth_buffer_float) DONE (i965, r600)
24 Framebuffer objects (GL_ARB_framebuffer_object) DONE (i965, r300, r600, swrast)
28 Per-buffer blend and masks (GL_EXT_draw_buffers2) DONE (i965, r600, swrast)
29 GL_EXT_texture_compression_rgtc DONE (i965, r300, r600, swrast
    [all...]
  /external/mesa3d/src/gallium/targets/dri-r600/
SConscript 13 r600,
28 env.Alias('dri-r600', module)
  /external/mesa3d/src/gallium/targets/pipe-loader/
pipe_r600.c 4 #include "r600/r600_public.h"
26 DRM_DRIVER_DESCRIPTOR("r600", "radeon", create_screen, NULL)
  /external/mesa3d/src/gallium/targets/va-r600/
target.c 4 #include "r600/r600_public.h"
24 DRM_DRIVER_DESCRIPTOR("r600", "radeon", create_screen, NULL)
  /external/mesa3d/src/gallium/targets/vdpau-r600/
target.c 4 #include "r600/r600_public.h"
24 DRM_DRIVER_DESCRIPTOR("r600", "radeon", create_screen, NULL)
  /external/mesa3d/src/gallium/targets/xorg-r600/
target.c 5 #include "r600/r600_public.h"
26 DRM_DRIVER_DESCRIPTOR("r600", "radeon", create_screen, NULL)
  /external/mesa3d/src/gallium/targets/xvmc-r600/
target.c 4 #include "r600/r600_public.h"
24 DRM_DRIVER_DESCRIPTOR("r600", "radeon", create_screen, NULL)
  /external/mesa3d/src/gallium/drivers/radeonsi/
r600_resource.c 55 void r600_init_context_resource_functions(struct r600_context *r600)
57 r600->context.get_transfer = u_get_transfer_vtbl;
58 r600->context.transfer_map = u_transfer_map_vtbl;
59 r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
60 r600->context.transfer_unmap = u_transfer_unmap_vtbl;
61 r600->context.transfer_destroy = u_transfer_destroy_vtbl;
62 r600->context.transfer_inline_write = u_default_transfer_inline_write;

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