| /toolchain/binutils/binutils-2.25/opcodes/ |
| i386-reg.tbl | 82 rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
83 rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
84 rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
85 rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
86 rsp, Reg64, 0, 4, Dw2Inval, 7
87 rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6
88 rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4
89 rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5
90 r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8
91 r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval,
[all...] |
| i386-opc.tbl | 26 mov, 2, 0x88, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixOk=3, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
30 mov, 2, 0xc6, 0x0, 1, 0, W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixOk=3, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
31 mov, 2, 0xb0, None, 1, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Imm64, Reg64 }
37 mov, 2, 0x8c, None, 1, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2, Reg16|Reg32|Reg64|RegMem }
39 mov, 2, 0x8c, None, 1, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg3, Reg16|Reg32|Reg64|RegMem }
41 mov, 2, 0x8e, None, 1, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64, SReg2 }
43 mov, 2, 0x8e, None, 1, Cpu386, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64, SReg3 }
48 mov, 2, 0xf20, None, 2, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Control, Reg64|RegMem }
50 mov, 2, 0xf21, None, 2, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Debug, Reg64|RegMem
[all...] |
| i386-gen.c | 261 "Reg64" },
325 "Reg64|Acc|Qword" },
527 BITFIELD (Reg64),
[all...] |
| i386-opc.h | 621 Reg64,
749 unsigned int reg64:1; member in struct:i386_operand_type::__anon75945
|
| ChangeLog-2008 | 479 into 32bit and 64bit. Remove Reg64|Qword and add
[all...] |
| ChangeLog-2013 | 223 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
[all...] |
| ChangeLog-2007 | 825 (Reg64): Likewise.
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| sjlj.ll | 57 ; X64: movq buf+8(%rip), %[[REG64:.*]]
59 ; X64: jmpq *%[[REG64]]
|
| /external/llvm/test/CodeGen/AArch64/ |
| func-argpassing.ll | 47 ; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}]
49 ; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64]
68 ; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16]
70 ; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64]
|
| /external/elfutils/libcpu/defs/ |
| i386 | 14 %mask {reg64} 3
98 `01100011,{mod}{reg64}{r_m}:movslq {mod}{r_m},{reg64}
421 00001111,00100000,11{ccc}{reg64}:mov {ccc},{reg64}
422 00001111,00100010,11{ccc}{reg64}:mov {reg64},{ccc}
423 00001111,00100001,11{ddd}{reg64}:mov {ddd},{reg64}
424 00001111,00100011,11{ddd}{reg64}:mov {reg64},{ddd
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.td | 487 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
495 def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> {
513 def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {
519 def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {
525 def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {
531 def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {
|
| AArch64FastISel.cpp | [all...] |
| /external/elfutils/tests/ |
| run-addrcfi.sh | 192 control reg64 (%mxcsr): undefined
258 control reg64 (%mxcsr): undefined
366 integer reg64 (cr): undefined
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-i386.c | [all...] |
| /external/v8/test/cctest/ |
| test-assembler-arm64.cc | [all...] |
| /toolchain/binutils/binutils-2.25/gas/ |
| ChangeLog-2004 | [all...] |
| ChangeLog-2007 | [all...] |
| ChangeLog-0001 | [all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| ChangeLog-9103 | 414 * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands.
[all...] |
