| /hardware/intel/img/psb_video/src/hwdefs/ |
| msvdx_offsets.h | 62 #define REGISTER_OFFSET(__group__, __reg__ ) ( (__group__##_##__reg__##_OFFSET) )
68 // #define REGISTER_OFFSET(__group__, __reg__ ) ( (__group__##_##__reg__##_OFFSET) + ( REG_##__group__##_OFFSET ) )
69 #define REGISTER_OFFSET(__group__, __reg__ ) ( (__group__##_##__reg__##_OFFSET) + ( REG_##__group__##_OFFSET ) + 0x04800000 )
|
| /hardware/intel/img/psb_video/src/mrst/ |
| psb_MPEG2MC.c | 292 psb_cmdbuf_reg_set(cmdbuf , REGISTER_OFFSET(MSVDX_CMDS, INTER_BLOCK_PREDICTION) + pred_offset, cmd);
340 psb_cmdbuf_reg_set(cmdbuf , REGISTER_OFFSET(MSVDX_CMDS, MOTION_VECTOR) , cmd);
346 psb_cmdbuf_reg_set(cmdbuf , REGISTER_OFFSET(MSVDX_CMDS, MOTION_VECTOR) , cmd);
353 psb_cmdbuf_reg_set(cmdbuf , REGISTER_OFFSET(MSVDX_CMDS, MOTION_VECTOR) + 0x10 , cmd);
370 psb_cmdbuf_reg_set(cmdbuf , REGISTER_OFFSET(MSVDX_CMDS, MOTION_VECTOR) , cmd);
384 psb_cmdbuf_reg_set(cmdbuf , REGISTER_OFFSET(MSVDX_CMDS, MOTION_VECTOR) + 0x10 , cmd);
395 psb_cmdbuf_reg_set(cmdbuf , REGISTER_OFFSET(MSVDX_CMDS, MOTION_VECTOR) + 0x40 , cmd);
407 psb_cmdbuf_reg_set(cmdbuf , REGISTER_OFFSET(MSVDX_CMDS, MOTION_VECTOR) + 0x50 , cmd);
425 psb_cmdbuf_reg_set(cmdbuf , REGISTER_OFFSET(MSVDX_CMDS, MOTION_VECTOR) , cmd);
434 psb_cmdbuf_reg_set(cmdbuf , REGISTER_OFFSET(MSVDX_CMDS, MOTION_VECTOR) + 0x10, cmd)
[all...] |
| psb_MPEG2.c | 902 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR0), ADDR0)
[all...] |
| psb_H264.c | [all...] |
| psb_MPEG4.c | [all...] |
| psb_VC1.c | [all...] |
| /hardware/intel/img/psb_video/src/ |
| pnw_MPEG2.c | [all...] |
| pnw_H264.c | [all...] |
| tng_VP8.c | 810 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0), ctx->reg_FE_PIC0);
811 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC1), ctx->reg_FE_PIC1);
812 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET(MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2), ctx->reg_FE_PIC2);
[all...] |
| tng_jpegdec.c | 681 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR0 ), reg_value);
688 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_VLC_TABLE_ADDR2 ), reg_value);
702 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_WIDTH0 ), reg_value);
716 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_VLC_TABLE_INITIAL_OPCODE0 ), reg_value);
863 psb_cmdbuf_reg_set(cmdbuf, REGISTER_OFFSET( MSVDX_VEC, CR_VEC_ENTDEC_FE_CONTROL ), reg_value);
[all...] |
| pnw_MPEG4.c | [all...] |
| pnw_VC1.c | [all...] |
| /external/v8/src/arm/ |
| macro-assembler-arm.cc | 867 int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize;
868 return MemOperand(sp, doubles_size + register_offset);
[all...] |
| /external/v8/src/ppc/ |
| macro-assembler-ppc.cc | 721 int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize; local
722 return MemOperand(sp, doubles_size + register_offset);
[all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 190 int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize; local
191 return MemOperand(sp, doubles_size + register_offset);
[all...] |
| /external/v8/src/mips64/ |
| macro-assembler-mips64.cc | 193 int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize; local
194 return MemOperand(sp, doubles_size + register_offset);
[all...] |
| /external/v8/src/s390/ |
| macro-assembler-s390.cc | 642 int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize; local
643 return MemOperand(sp, doubles_size + register_offset);
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-mips.c | 6431 int register_offset; member in struct:fix_24k_store_info
[all...] |
