| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vsub.ll | 66 ;CHECK: rsubhn.8b
69 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
75 ;CHECK: rsubhn.4h
78 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
84 ;CHECK: rsubhn.2s
87 %tmp3 = call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
93 ;CHECK: rsubhn.8b
95 %vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
96 %vrsubhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
103 ;CHECK: rsubhn.4
[all...] |
| arm64-vecFold.ll | 111 ; CHECK: rsubhn.8b v0, v0, v1
114 %vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a0, <8 x i16> %a1) nounwind
115 %vrsubhn2.i10 = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %b0, <8 x i16> %b1) nounwind
144 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
|
| arm64-neon-3vdiff.ll | 41 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>)
43 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>)
45 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>)
[all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-3vdiff.s | 401 rsubhn v0.8b, v1.8h, v2.8h
402 rsubhn v0.4h, v1.4s, v2.4s
403 rsubhn v0.2s, v1.2d, v2.2d
405 // CHECK: rsubhn v0.8b, v1.8h, v2.8h // encoding: [0x20,0x60,0x22,0x2e]
406 // CHECK: rsubhn v0.4h, v1.4s, v2.4s // encoding: [0x20,0x60,0x62,0x2e]
407 // CHECK: rsubhn v0.2s, v1.2d, v2.2d // encoding: [0x20,0x60,0xa2,0x2e]
|
| neon-diagnostics.s | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.h | [all...] |
| simulator-a64.h | [all...] |
| disasm-a64.cc | [all...] |
| assembler-a64.h | [all...] |
| logic-a64.cc | 3373 LogicVRegister Simulator::rsubhn(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| simulator-a64.cc | [all...] |
| assembler-a64.cc | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | 639 #include "traces/a64/sim-rsubhn-2s-trace-a64.h"
640 #include "traces/a64/sim-rsubhn-4h-trace-a64.h"
641 #include "traces/a64/sim-rsubhn-8b-trace-a64.h"
[all...] |
| test-disasm-a64.cc | [all...] |
| test-simulator-a64.cc | [all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-intrinsics.c | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| fp_and_simd.stdout.exp | [all...] |
| /prebuilts/gcc/darwin-x86/aarch64/aarch64-linux-android-4.9/lib/gcc/aarch64-linux-android/4.9/include/ |
| arm_neon.h | [all...] |
| /prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/lib/gcc/aarch64-linux-android/4.9/include/ |
| arm_neon.h | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-dis-2.c | [all...] |
| aarch64-tbl.h | 1324 {"rsubhn", 0x2e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| neon-instructions.txt | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | [all...] |
