| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| arm-idiv-bad.s | 4 sdiv r0, r0, r0
|
| armv7-a+idiv.s | 8 sdiv r0, r1, r2
14 sdiv r0, r1, r2
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| arm-idiv-bad.l | 2 [^:]*:4: Error: selected processor does not support ARM mode `sdiv r0,r0,r0'
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| arm-idiv.s | 8 sdiv r0, r0, r0 label
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| /external/llvm/test/CodeGen/PowerPC/ |
| ppc64-r2-alloc.ll | 7 %div = sdiv i32 %a, %d
8 %div1 = sdiv i32 %div, %d
9 %div2 = sdiv i32 %div1, %d
10 %div3 = sdiv i32 %div2, %d
11 %div4 = sdiv i32 %div3, %d
12 %div5 = sdiv i32 %div4, %d
13 %div6 = sdiv i32 %div5, %d
14 %div7 = sdiv i32 %div6, %d
15 %div8 = sdiv i32 %div7, %d
16 %div9 = sdiv i32 %div8, %
[all...] |
| /art/runtime/interpreter/mterp/arm64/ |
| op_div_int.S | 1 %include "arm64/binop.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"}
|
| op_div_int_2addr.S | 1 %include "arm64/binop2addr.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"}
|
| op_div_int_lit16.S | 1 %include "arm64/binopLit16.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"}
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| op_div_int_lit8.S | 1 %include "arm64/binopLit8.S" {"instr":"sdiv w0, w0, w1", "chkzero":"1"}
|
| op_div_long.S | 1 %include "arm64/binopWide.S" {"instr":"sdiv x0, x1, x2", "chkzero":"1"}
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| op_div_long_2addr.S | 1 %include "arm64/binopWide2addr.S" {"instr":"sdiv x0, x0, x1", "chkzero":"1"}
|
| op_rem_int.S | 1 %include "arm64/binop.S" {"preinstr":"sdiv w2, w0, w1", "instr":"msub w0, w2, w1, w0", "chkzero":"1"}
|
| op_rem_int_2addr.S | 1 %include "arm64/binop2addr.S" {"preinstr":"sdiv w2, w0, w1", "instr":"msub w0, w2, w1, w0", "chkzero":"1"}
|
| op_rem_int_lit16.S | 1 %include "arm64/binopLit16.S" {"preinstr":"sdiv w3, w0, w1", "instr":"msub w0, w3, w1, w0", "chkzero":"1"}
|
| op_rem_int_lit8.S | 1 %include "arm64/binopLit8.S" {"preinstr":"sdiv w3, w0, w1", "instr":"msub w0, w3, w1, w0", "chkzero":"1"}
|
| op_rem_long.S | 1 %include "arm64/binopWide.S" {"preinstr":"sdiv x3, x1, x2","instr":"msub x0, x3, x2, x1", "chkzero":"1"}
|
| op_rem_long_2addr.S | 1 %include "arm64/binopWide2addr.S" {"preinstr":"sdiv x3, x0, x1", "instr":"msub x0, x3, x1, x0", "chkzero":"1"}
|
| /external/llvm/test/Analysis/CostModel/X86/ |
| div.ll | 7 ; SSE2: cost of 320 {{.*}} sdiv
8 %a0 = sdiv <16 x i8> undef, undef
9 ; SSE2: cost of 160 {{.*}} sdiv
10 %a1 = sdiv <8 x i16> undef, undef
11 ; SSE2: cost of 80 {{.*}} sdiv
12 %a2 = sdiv <4 x i32> undef, undef
13 ; SSE2: cost of 40 {{.*}} sdiv
14 %a3 = sdiv <2 x i32> undef, undef
21 ; AVX2: cost of 640 {{.*}} sdiv
22 %a0 = sdiv <32 x i8> undef, unde
[all...] |
| /external/llvm/test/Transforms/InstCombine/ |
| 2008-02-16-SDivOverflow2.ll | 1 ; RUN: opt < %s -instcombine -S | grep "sdiv i8 \%a, 9"
5 %tmp1 = sdiv i8 %a, -3
6 %tmp2 = sdiv i8 %tmp1, -3
|
| 2008-05-22-IDivVector.ll | 4 %A = sdiv <3 x i8> %i, %i
|
| /external/llvm/test/Transforms/InstSimplify/ |
| 2011-02-01-Vector.ll | 3 define <2 x i32> @sdiv(<2 x i32> %x) {
4 ; CHECK-LABEL: @sdiv(
5 %div = sdiv <2 x i32> %x, <i32 1, i32 1>
|
| /external/llvm/test/Transforms/ConstProp/ |
| 2007-02-23-sdiv.ll | 4 @G = global i32 sdiv (i32 0, i32 -1)
|
| /external/llvm/test/Analysis/Lint/ |
| check-zero-divide.ll | 4 %b = sdiv <2 x i32> %a, <i32 5, i32 8>
25 ; CHECK-NEXT: %b = sdiv i32 %a, 0
26 %b = sdiv i32 %a, 0
32 ; CHECK-NEXT: %b = sdiv i32 %a, 0
33 %b = sdiv i32 %a, zeroinitializer
39 ; CHECK-NEXT: %b = sdiv <2 x i32> %a, <i32 0, i32 5>
40 %b = sdiv <2 x i32> %a, <i32 0, i32 5>
46 ; CHECK-NEXT: %b = sdiv <2 x i32> %a, <i32 4, i32 0>
47 %b = sdiv <2 x i32> %a, <i32 4, i32 0>
53 ; CHECK-NEXT: %b = sdiv <2 x i32> %a, zeroinitialize
[all...] |
| /external/clang/test/CodeGen/ |
| 2005-01-02-PointerDifference.c | 3 // CHECK: sdiv exact
|
| /external/llvm/test/CodeGen/Generic/ |
| div-neg-power-2.ll | 4 %Y = sdiv i32 %X, -2 ; <i32> [#uses=1]
|
