| /external/llvm/test/CodeGen/Hexagon/ |
| brev_st.ll | 23 %shr2 = lshr i32 %conv, 1
27 %sub = sub i32 13, %shr2
59 %shr2 = lshr i32 %conv, 1
63 %sub = sub i32 15, %shr2
77 %shr2 = lshr i32 %conv, 1
81 %sub = sub i32 15, %shr2
95 %shr2 = lshr i32 %conv, 1
99 %sub = sub nsw i32 16, %shr2
|
| circ_st.ll | 22 %shr2 = lshr i32 %conv, 1
26 %or = or i32 %shr2, 33554432
56 %shr2 = and i32 %conv, 65534
60 %or = or i32 %shr2, 50331648
73 %shr2 = and i32 %conv, 65534
77 %or = or i32 %shr2, 50331648
|
| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| pr23510.ll | 20 %shr2 = lshr i64 %tmp1, 4
21 store i64 %shr2, i64* %arrayidx1, align 8
|
| /external/llvm/test/CodeGen/ARM/ |
| bfx.ll | 42 %shr2 = and i32 %and1, 255
46 %arrayidx5 = getelementptr inbounds i32, i32* %ctx, i32 %shr2
|
| /external/llvm/test/CodeGen/PowerPC/ |
| rm-zext.ll | 9 %shr2 = lshr i32 %mul, 5
10 ret i32 %shr2
|
| ctrloop-intrin.ll | 48 %shr2 = lshr i64 %2, 63
49 %conv3 = trunc i64 %shr2 to i32
|
| /external/llvm/test/CodeGen/X86/ |
| change-compare-stride-trickiness-2.ll | 26 %shr2.i = lshr i64 %pa.0642, 18 ; <i64> [#uses=0]
51 %shr2.i = lshr i32 %pa.0642, 18 ; <i64> [#uses=0]
|
| x86-shifts.ll | 54 define <2 x i64> @shr2(<2 x i64> %A) nounwind {
56 ; CHECK: shr2
|
| /external/libhevc/common/arm/ |
| ihevc_intra_pred_luma_dc.s | 235 vqshrun.s16 d2, q10, #2 @columns shr2 movn (prol)
241 vqshrun.s16 d3, q11, #2 @rows shr2 movn (prol)
261 vqshrun.s16 d4, q13, #2 @columns shr2 movn (prol extra)
319 vqshrun.s16 d3, q11, #2 @rows shr2 movn (prol)
469 vqshrun.s16 d2, q10, #2 @columns shr2 movn (prol)
472 vqshrun.s16 d3, q11, #2 @rows shr2 movn (prol)
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-bitfield-extract.ll | 256 %shr2 = lshr i32 %shl, 4
257 store i32 %shr2, i32* %y, align 8
279 %shr2 = lshr i64 %shl, 4
280 store i64 %shr2, i64* %y, align 8
366 %shr2 = lshr i32 %shl, 4
367 store i32 %shr2, i32* %y, align 8
395 %shr2 = lshr i64 %shl, 4
396 store i64 %shr2, i64* %y, align 8
|
| /external/llvm/test/Transforms/InstCombine/ |
| shift.ll | 712 %shr2 = lshr i32 %x, 1
713 %shl = shl i32 %shr2, 4
722 %shr2 = lshr i32 %x, 1
723 %shl = shl i32 %shr2, 4
731 %shr2 = lshr i32 %x, 1
732 %shl = shl i32 %shr2, 4
736 ; CHECK: shl i32 %shr2, 4
|
| /art/test/538-checker-embed-constants/src/ |
| Main.java | 349 /// CHECK-START-ARM: long Main.shr2(long) disassembly (after)
354 /// CHECK-START-ARM: long Main.shr2(long) disassembly (after)
357 public static long shr2(long arg) { method in class:Main
541 assertLongEquals(shr2(longArg), 0x048d159e21d950c8L); method
547 assertLongEquals(shr2(~longArg), 0xfb72ea61de26af37L); method
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic6x/ |
| insns-bad-1.s | 1028 shr2 .L1 a0,a0,a0
1029 shr2 .L1 a0,0,a0
1030 shr2 .S1 a0,a0
1031 shr2 .S1 a1,b0,a0
1032 shr2 .S2X b0,b0,b0
1033 shr2 .S1 a0,-1,a0
1034 shr2 .S1 a0,32,a0
|
| insns-c674x.s | 1168 shr2 .S1 a1,a2,a3
1169 [!b0] shr2 .S1X b4,a5,a6
1170 [a1] shr2 .S2 b7,b8,b9
1171 shr2 .S2X a10,b11,b12
1172 shr2 .S1 a1,31,a3
1173 [b1] shr2 .S1X b4,0,a6
1174 [!a1] shr2 .S2 b7,5,b9
1175 shr2 .S2X a10,25,b12
[all...] |
| insns-bad-1.l | [all...] |
| insns-c674x.d | [all...] |
| /frameworks/av/media/libstagefright/httplive/ |
| M3UParser.cpp | [all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| tic6x-opcode-table.h | [all...] |
