/external/libhevc/common/arm64/ |
ihevc_inter_pred_chroma_vert_w16inp.s | 158 sqshrn v0.4h, v0.4s,#6 //right shift 159 sqshrn v30.4h, v7.4s,#6 //right shift 211 sqshrn v30.4h, v30.4s,#6 //right shift 221 sqshrn v28.4h, v28.4s,#6 //right shift 234 sqshrn v26.4h, v26.4s,#6 //right shift 248 sqshrn v24.4h, v24.4s,#6 //right shift 262 sqshrn v30.4h, v30.4s,#6 //right shift 275 sqshrn v28.4h, v28.4s,#6 //right shift 289 sqshrn v26.4h, v26.4s,#6 //right shift 305 sqshrn v24.4h, v24.4s,#6 //right shif [all...] |
ihevc_inter_pred_chroma_vert_w16inp_w16out.s | 158 sqshrn v0.4h, v0.4s,#6 //right shift 159 sqshrn v30.4h, v7.4s,#6 //right shift 209 sqshrn v30.4h, v30.4s,#6 //right shift 219 sqshrn v28.4h, v28.4s,#6 //right shift 232 sqshrn v26.4h, v26.4s,#6 //right shift 245 sqshrn v24.4h, v24.4s,#6 //right shift 258 sqshrn v30.4h, v30.4s,#6 //right shift 270 sqshrn v28.4h, v28.4s,#6 //right shift 283 sqshrn v26.4h, v26.4s,#6 //right shift 298 sqshrn v24.4h, v24.4s,#6 //right shif [all...] |
ihevc_inter_pred_filters_luma_vert_w16inp.s | 185 sqshrn v19.4h, v19.4s,#6 199 sqshrn v20.4h, v20.4s,#6 217 sqshrn v21.4h, v21.4s,#6 242 sqshrn v30.4h, v30.4s,#6 259 sqshrn v19.4h, v19.4s,#6 285 sqshrn v20.4h, v20.4s,#6 305 sqshrn v21.4h, v21.4s,#6 326 sqshrn v30.4h, v30.4s,#6 340 sqshrn v19.4h, v19.4s,#6 353 sqshrn v20.4h, v20.4s,# [all...] |
ihevc_deblk_luma_horz.s | 531 sqshrn v14.8b, v14.8h,#1 564 sqshrn v14.8b, v14.8h,#1
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/external/libhevc/decoder/arm64/ |
ihevcd_fmt_conv_420sp_to_rgba8888.s | 212 sqshrn v5.4h, v5.4s,#13 ////D8 = (U-128)*C4>>13 4 16-BIT VALUES 217 sqshrn v7.4h, v20.4s,#13 ////D10 = (V-128)*C1>>13 4 16-BIT VALUES 222 sqshrn v12.4h, v12.4s,#13 ////D12 = [(U-128)*C2 + (V-128)*C3]>>13 4 16-BIT VALUES 375 sqshrn v5.4h, v5.4s,#13 ////D8 = (U-128)*C4>>13 4 16-BIT VALUES 380 sqshrn v7.4h, v20.4s,#13 ////D10 = (V-128)*C1>>13 4 16-BIT VALUES 385 sqshrn v12.4h, v12.4s,#13 ////D12 = [(U-128)*C2 + (V-128)*C3]>>13 4 16-BIT VALUES
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/external/llvm/test/MC/AArch64/ |
neon-scalar-shift-imm.s | 124 sqshrn b10, h15, #5 125 sqshrn h17, s10, #4 126 sqshrn s18, d10, #31 128 // CHECK: sqshrn b10, h15, #5 // encoding: [0xea,0x95,0x0b,0x5f] 129 // CHECK: sqshrn h17, s10, #4 // encoding: [0x51,0x95,0x1c,0x5f] 130 // CHECK: sqshrn s18, d10, #31 // encoding: [0x52,0x95,0x21,0x5f]
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arm64-advsimd.s | [all...] |
neon-simd-shift.s | 332 sqshrn v0.8b, v1.8h, #3 333 sqshrn v0.4h, v1.4s, #3 334 sqshrn v0.2s, v1.2d, #3 339 // CHECK: sqshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x94,0x0d,0x0f] 340 // CHECK: sqshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x94,0x1d,0x0f] 341 // CHECK: sqshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x94,0x3d,0x0f]
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/external/llvm/test/CodeGen/AArch64/ |
arm64-neon-simd-shift.ll | 435 %vqshrn = tail call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %b, i32 3) 446 %vqshrn = tail call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %b, i32 9) 458 %vqshrn = tail call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %b, i32 19) 584 declare <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16>, i32) 586 declare <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32>, i32) 588 declare <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64>, i32)
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arm64-vshift.ll | 743 ; CHECK: sqshrn {{s[0-9]+}}, d0, #1 744 %tmp = call i32 @llvm.aarch64.neon.sqshrn.i32(i64 %A, i32 1) 750 ;CHECK: sqshrn.8b v0, {{v[0-9]+}}, #1 752 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1) 758 ;CHECK: sqshrn.4h v0, {{v[0-9]+}}, #1 760 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1) 766 ;CHECK: sqshrn.2s v0, {{v[0-9]+}}, #1 768 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1) 778 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1) 788 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1 [all...] |
/external/libavc/common/armv8/ |
ih264_deblk_luma_av8.s | 167 sqshrn v29.8b, v28.8h, #1 // 168 sqshrn v28.8b, v10.8h, #1 //Q14 = i_macro_p1 175 sqshrn v31.8b, v30.8h, #1 // 176 sqshrn v30.8b, v4.8h, #1 //Q15 = i_macro_q1 568 sqshrn v24.8b, v24.8h, #1 //((p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)) >> 1) L 569 sqshrn v25.8b, v26.8h, #1 //((p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)) >> 1) H 589 sqshrn v18.8b, v18.8h, #1 //((q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)) >> 1) L 591 sqshrn v19.8b, v20.8h, #1 //((q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)) >> 1) H [all...] |
/external/valgrind/none/tests/arm64/ |
fp_and_simd.c | [all...] |
/external/llvm/test/MC/Disassembler/AArch64/ |
arm64-advsimd.txt | [all...] |
/frameworks/rs/cpu_ref/ |
rsCpuIntrinsics_advsimd_Resize.S | 73 sqshrn \dstlo, v12.4s, #8 + (16 - VERTBITS) 95 sqshrn \dst, v12.4s, #8 + (16 - VERTBITS)
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/external/libjpeg-turbo/simd/ |
jsimd_arm64_neon.S | [all...] |
/external/vixl/test/ |
test-simulator-traces-a64.h | [all...] |
test-disasm-a64.cc | [all...] |
test-simulator-a64.cc | [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
aarch64-dis-2.c | [all...] |
/external/vixl/doc/ |
supported-instructions.md | [all...] |
/external/vixl/src/vixl/a64/ |
disasm-a64.cc | [all...] |
macro-assembler-a64.h | [all...] |
simulator-a64.h | [all...] |
simulator-a64.cc | [all...] |
/external/valgrind/VEX/priv/ |
host_arm64_defs.c | 775 case ARM64vecshi_SQSHRN2SD: *nm = "sqshrn"; *ar = "2sd"; return; 776 case ARM64vecshi_SQSHRN4HS: *nm = "sqshrn"; *ar = "4hs"; return; 777 case ARM64vecshi_SQSHRN8BH: *nm = "sqshrn"; *ar = "8bh"; return; [all...] |