/external/llvm/lib/Target/AMDGPU/ |
R600InstrFormats.td | 97 bits<1> src1_neg; 100 let Word0{25} = src1_neg;
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R600ExpandSpecialInstrs.cpp | 343 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_neg);
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R600InstrInfo.cpp | [all...] |
R600Instructions.td | 111 let src1_neg = 0; 140 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel, 146 "$src1_neg$src1_abs$src1$src1_abs$src1_rel, " 179 R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel, 185 "$src1_neg$src1$src1_rel, " [all...] |
EvergreenInstructions.td | 387 let src1_neg = 0;
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R600ISelLowering.cpp | [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
radeon_optimize.c | 568 unsigned src1_neg = inst_add->U.I.SrcReg[1].Negate & dstmask; local 586 if (inst_add->U.I.SrcReg[1].Negate && src1_neg != dstmask)
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/external/mesa3d/src/gallium/drivers/radeon/ |
R600Instructions.td | 69 bits<1> SRC1_NEG = 0; [all...] |