| /external/libavc/common/armv8/ |
| ih264_ihadamard_scaling_av8.s | 111 ssubl v6.4s, v1.4h, v2.4h //x2 = x5 - x6
112 ssubl v7.4s, v0.4h, v3.4h //x3 = x4 - x7
225 ssubl v4.4s, v0.4h, v1.4h //i4_x1 = i4_x4 - i4_x5;...x3
|
| ih264_resi_trans_quant_av8.s | 530 ssubl v6.4s, v1.4h, v2.4h //x2 = x5 - x6;
531 ssubl v7.4s, v0.4h, v3.4h //x3 = x4 - x7;
678 ssubl v3.4s, v0.4h, v1.4h //x1 = x4 - x5; x3 = x6 - x7;
|
| ih264_iquant_itrans_recon_av8.s | 655 ssubl v22.4s, v13.4h, v11.4h
661 ssubl v26.4s, v15.4h, v9.4h
|
| /external/libhevc/common/arm64/ |
| ihevc_itrans_recon_4x4.s | 150 ssubl v17.4s, v0.4h, v2.4h //pi2_src[0] - pi2_src[2]
184 ssubl v17.4s, v0.4h, v2.4h //pi2_src[0] - pi2_src[2]
|
| /external/llvm/test/MC/AArch64/ |
| neon-3vdiff.s | 49 ssubl v0.8h, v1.8b, v2.8b
50 ssubl v0.4s, v1.4h, v2.4h
51 ssubl v0.2d, v1.2s, v2.2s
53 // CHECK: ssubl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x20,0x22,0x0e]
54 // CHECK: ssubl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x20,0x62,0x0e]
55 // CHECK: ssubl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x20,0xa2,0x0e]
|
| neon-diagnostics.s | [all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vsub.ll | 127 ;CHECK: ssubl.8h
138 ;CHECK: ssubl.4s
149 ;CHECK: ssubl.2d
|
| arm64-neon-3vdiff.ll | 301 ; CHECK: ssubl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
311 ; CHECK: ssubl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
321 ; CHECK: ssubl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
[all...] |
| /external/libjpeg-turbo/simd/ |
| jsimd_arm64_neon.S | 315 ssubl v6.4s, ROW0L.4h, ROW4L.4h
397 ssubl v6.4s, ROW0R.4h, ROW4R.4h
466 ssubl v6.4s, ROW0L.4h, ROW0R.4h /* ROW4L.4h <-> ROW0R.4h */
515 ssubl v6.4s, ROW4L.4h, ROW4R.4h /* ROW4L.4h <-> ROW0R.4h */
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedCyclone.td | 412 // SADDL,SSUBL,UADDL,USUBL
|
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.h | [all...] |
| simulator-a64.h | [all...] |
| disasm-a64.cc | [all...] |
| assembler-a64.h | [all...] |
| logic-a64.cc | 2923 LogicVRegister Simulator::ssubl(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| simulator-a64.cc | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| test-simulator-a64.cc | [all...] |
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| scale_neon64.cc | 623 "ssubl v16.4s, v5.4h, v4.4h \n"
[all...] |
| /external/libyuv/files/source/ |
| scale_neon64.cc | 623 "ssubl v16.4s, v5.4h, v4.4h \n"
[all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-dis-2.c | [all...] |
| aarch64-tbl.h | 1284 {"ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
[all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-intrinsics.c | [all...] |
