| /external/llvm/test/CodeGen/AArch64/ |
| arm64-umaxv.ll | 5 ; CHECK: umaxv.8b b[[REG:[0-9]+]], v0
10 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) nounwind
28 ; CHECK: umaxv.4h h[[REG:[0-9]+]], v0
33 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) nounwind
49 ; CHECK: umaxv.8h h[[REG:[0-9]+]], v0
54 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) nounwind
70 ; CHECK: umaxv.16b b[[REG:[0-9]+]], v0
75 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) nounwind
91 ; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
95 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2
[all...] |
| arm64-neon-across.ll | 41 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>)
43 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>)
45 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>)
53 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>)
55 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>)
185 ; CHECK: umaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
187 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a)
188 %0 = trunc i32 %umaxv.i to i8
194 ; CHECK: umaxv h{{[0-9]+}}, {{v[0-9]+}}.4
[all...] |
| arm64-vecCmpBr.ll | 58 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
66 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
82 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
89 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
105 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
112 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
128 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
135 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
195 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) #2
197 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) #
[all...] |
| aarch64-minmaxv.ll | 78 ; CHECK: umaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
100 ; CHECK: umaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
119 ; CHECK: umaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
135 ; CHECK-NOT: umaxv
324 ; CHECK: umaxv {{h[0-9]+}}, [[V0]]
349 ; CHECK-NEXT: umaxv {{s[0-9]+}}, [[V0]]
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| advsimd-across.d | 23 3c: 2e30abe7 umaxv b7, v31.8b
24 40: 6e30abe7 umaxv b7, v31.16b
25 44: 2e70abe7 umaxv h7, v31.4h
26 48: 6e70abe7 umaxv h7, v31.8h
27 4c: 6eb0abe7 umaxv s7, v31.4s
|
| advsimd-across.s | 36 .irp op, smaxv, umaxv, sminv, uminv, addv
|
| /external/llvm/test/MC/AArch64/ |
| neon-across.s | 57 umaxv b0, v1.8b
58 umaxv b0, v1.16b
59 umaxv h0, v1.4h
60 umaxv h0, v1.8h
61 umaxv s0, v1.4s
63 // CHECK: umaxv b0, v1.8b // encoding: [0x20,0xa8,0x30,0x2e]
64 // CHECK: umaxv b0, v1.16b // encoding: [0x20,0xa8,0x30,0x6e]
65 // CHECK: umaxv h0, v1.4h // encoding: [0x20,0xa8,0x70,0x2e]
66 // CHECK: umaxv h0, v1.8h // encoding: [0x20,0xa8,0x70,0x6e]
67 // CHECK: umaxv s0, v1.4s // encoding: [0x20,0xa8,0xb0,0x6e
[all...] |
| /external/clang/test/CodeGen/ |
| arm64_vecCmpBr.c | 37 // CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
50 // CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
63 // CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
76 // CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
|
| aarch64-neon-across.c | 84 // CHECK: umaxv {{b[0-9]+}}, {{v[0-9]+}}.8b
90 // CHECK: umaxv {{h[0-9]+}}, {{v[0-9]+}}.4h
114 // CHECK: umaxv {{b[0-9]+}}, {{v[0-9]+}}.16b
120 // CHECK: umaxv {{h[0-9]+}}, {{v[0-9]+}}.8h
126 // CHECK: umaxv {{s[0-9]+}}, {{v[0-9]+}}.4s
|
| arm64_vMaxMin.c | 123 // CHECK: call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(
|
| /external/opencv3/modules/core/test/ocl/ |
| test_arithm.cpp | 1161 double minv, maxv, uminv, umaxv; local
1166 OCL_ON(cv::minMaxIdx(usrc2_roi, &uminv, &umaxv));
1169 EXPECT_DOUBLE_EQ(maxv, umaxv);
1174 OCL_ON(cv::minMaxIdx(usrc2_roi, &uminv, &umaxv, up1, up2, noArray()));
1177 EXPECT_DOUBLE_EQ(maxv, umaxv);
1197 double minv, maxv, uminv, umaxv; local
1200 OCL_ON(cv::minMaxIdx(usrc2_roi, &uminv, &umaxv, up1, up2, umask_roi));
1203 EXPECT_DOUBLE_EQ(maxv, umaxv);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 156 UMAXV,
|
| AArch64SchedCyclone.td | 419 def : InstRW<[CyWriteV3], (instregex "SMAXv","SMINv","UMAXv","UMINv",
|
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | 595 "umaxv s8, v7.4s ; "
599 printf("UMAXV v8, v7.4s ");
612 "umaxv h8, v7.8h ; "
616 printf("UMAXV h8, v7.8h ");
629 "umaxv h8, v7.4h ; "
633 printf("UMAXV h8, v7.4h ");
646 "umaxv b8, v7.16b ; "
650 printf("UMAXV b8, v7.16b ");
663 "umaxv b8, v7.8b ; "
667 printf("UMAXV b8, v7.8b ")
[all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | [all...] |
| test-disasm-a64.cc | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.h | [all...] |
| /external/bison/build-aux/ |
| config.guess | [all...] |
| /external/c-ares/ |
| config.guess | [all...] |
| /external/cmockery/cmockery_0_1_2/ |
| config.guess | [all...] |
| /external/e2fsprogs/config/ |
| config.guess | [all...] |
| /external/fec/ |
| config.guess | [all...] |
| /external/google-tv-pairing-protocol/cpp/ |
| config.guess | [all...] |
| /external/icu/icu4c/source/ |
| config.guess | [all...] |
