| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| neon-ldst-align-bad.s | 0 vld1.8 {d0}, [r0 :128]
2 vld1.8 {q0}, [r0 :256]
|
| neon-addressing-bad.s | 3 VLD1.8 {d0}, 1f
5 VLD1.8 {D0}, R0
6 VLD1.8 {Q1}, R0
7 VLD1.8 {D0}, [PC]
8 VLD1.8 {D0}, [PC, #0]
17 VLD1.8 {Q0}, [R0, #8]
18 VLD1.8 {Q0}, [R0, #8]!
19 VLD1.8 {Q0}, [R0, R1]
20 VLD1.8 {Q0}, [R0, R1]!
22 VLD1.8 {d0}, 2
[all...] |
| macro-vld1.s | 9 sfi_breg r0, vld1.8 {d0}, [\B]
10 sfi_breg r0, vld1.8 { d0 }, [\B]
|
| macro-vld1.d | 8 \s*0:\s+f420070f\s+vld1.8\s+{d0},\s*\[r0\]
9 \s*4:\s+f420070f\s+vld1.8\s+{d0},\s*\[r0\]
|
| neon-ldst-align-bad.l | 2 [^:]*:1: Error: bad alignment -- `vld1.8 {d0},\[r0:128\]'
3 [^:]*:2: Error: bad alignment -- `vld1.8 {q0},\[r0:256\]'
|
| neon-ldst-es-bad.s | 2 vld1.64 {d0[1]}, [r0]
3 vld1.64 {d0[]}, [r0]
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/neon/ |
| sad8_neon.asm | 28 vld1.8 {d0}, [r0], r1
29 vld1.8 {d8}, [r2], r3
31 vld1.8 {d2}, [r0], r1
32 vld1.8 {d10}, [r2], r3
36 vld1.8 {d4}, [r0], r1
37 vld1.8 {d12}, [r2], r3
41 vld1.8 {d6}, [r0], r1
42 vld1.8 {d14}, [r2], r3
46 vld1.8 {d0}, [r0], r1
47 vld1.8 {d8}, [r2], r
[all...] |
| sad16_neon.asm | 27 vld1.8 {q0}, [r0], r1
28 vld1.8 {q4}, [r2], r3
30 vld1.8 {q1}, [r0], r1
31 vld1.8 {q5}, [r2], r3
36 vld1.8 {q2}, [r0], r1
37 vld1.8 {q6}, [r2], r3
42 vld1.8 {q3}, [r0], r1
43 vld1.8 {q7}, [r2], r3
49 vld1.8 {q0}, [r0], r1
50 vld1.8 {q4}, [r2], r
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/encoder/arm/neon/ |
| subtract_neon.asm | 36 vld1.8 {d0}, [r3], r6 ;load src
37 vld1.8 {d1}, [r7], r2 ;load pred
38 vld1.8 {d2}, [r3], r6
39 vld1.8 {d3}, [r7], r2
40 vld1.8 {d4}, [r3], r6
41 vld1.8 {d5}, [r7], r2
42 vld1.8 {d6}, [r3], r6
43 vld1.8 {d7}, [r7], r2
74 vld1.8 {q0}, [r1], r2 ;load src
75 vld1.8 {q1}, [r3], r4 ;load pre
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| v8_IT_1.ll | 9 %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %bar, i32 1)
12 %vld1. = select i1 %tobool, <16 x i8> %vld1, <16 x i8> zeroinitializer
13 ret <16 x i8> %vld1.
16 declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* , i32 )
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/comm/src/ |
| omxVCCOMM_Copy16x16_s.s | 48 VLD1 {X0,X1},[pSrc@128],step ;// Load 16 bytes from 16 byte aligned pSrc and pSrc=pSrc + step after loading
49 VLD1 {X2,X3},[pSrc@128],step
50 VLD1 {X4,X5},[pSrc@128],step
51 VLD1 {X6,X7},[pSrc@128],step
57 VLD1 {X0,X1},[pSrc@128],step
58 VLD1 {X2,X3},[pSrc@128],step
59 VLD1 {X4,X5},[pSrc@128],step
60 VLD1 {X6,X7},[pSrc@128],step
66 VLD1 {X0,X1},[pSrc@128],step
67 VLD1 {X2,X3},[pSrc@128],ste
[all...] |
| omxVCCOMM_Copy8x8_s.s | 45 VLD1 {X0},[pSrc],step ;// Load 8 bytes from 8 byte aligned pSrc, pSrc=pSrc+step after load
46 VLD1 {X1},[pSrc],step
47 VLD1 {X2},[pSrc],step
48 VLD1 {X3},[pSrc],step
53 VLD1 {X0},[pSrc],step
54 VLD1 {X1},[pSrc],step
55 VLD1 {X2},[pSrc],step
56 VLD1 {X3},[pSrc],step
|
| /external/libavc/common/arm/ |
| ih264_inter_pred_luma_bilinear_a9q.s | 136 vld1.8 {q0}, [r0], r3 @// Load row0 ;src1
137 vld1.8 {q2}, [r1], r4 @// Load row0 ;src2
138 vld1.8 {q1}, [r0], r3 @// Load row1 ;src1
140 vld1.8 {q3}, [r1], r4 @// Load row1 ;src2
142 vld1.8 {q4}, [r0], r3 @// Load row2 ;src1
144 vld1.8 {q5}, [r0], r3 @// Load row3 ;src1
146 vld1.8 {q6}, [r1], r4 @// Load row2 ;src2
148 vld1.8 {q7}, [r1], r4 @// Load row3 ;src2
159 vld1.8 {q0}, [r0], r3 @// Load row4 ;src1
161 vld1.8 {q1}, [r0], r3 @// Load row5 ;src
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| vpx_convolve_avg_neon_asm.asm | 36 vld1.8 {q0-q1}, [r0]!
37 vld1.8 {q2-q3}, [r0], lr
39 vld1.8 {q8-q9}, [r6@128]!
40 vld1.8 {q10-q11}, [r6@128], r4
52 vld1.8 {q0-q1}, [r0], r1
53 vld1.8 {q2-q3}, [r0], r1
54 vld1.8 {q8-q9}, [r6@128], r3
55 vld1.8 {q10-q11}, [r6@128], r3
71 vld1.8 {q0}, [r0], r1
72 vld1.8 {q1}, [r0], r
[all...] |
| idct16x16_1_add_neon.asm | 52 vld1.64 {d2}, [r1], r0
53 vld1.64 {d3}, [r1], r2
54 vld1.64 {d4}, [r1], r0
55 vld1.64 {d5}, [r1], r2
56 vld1.64 {d6}, [r1], r0
57 vld1.64 {d7}, [r1], r2
58 vld1.64 {d16}, [r1], r0
59 vld1.64 {d17}, [r1], r2
88 vld1.64 {d2}, [r1], r0
89 vld1.64 {d3}, [r1], r
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/ |
| vp9_avg_neon.asm | 36 vld1.8 {q0-q1}, [r0]!
37 vld1.8 {q2-q3}, [r0], lr
39 vld1.8 {q8-q9}, [r6@128]!
40 vld1.8 {q10-q11}, [r6@128], r4
52 vld1.8 {q0-q1}, [r0], r1
53 vld1.8 {q2-q3}, [r0], r1
54 vld1.8 {q8-q9}, [r6@128], r3
55 vld1.8 {q10-q11}, [r6@128], r3
71 vld1.8 {q0}, [r0], r1
72 vld1.8 {q1}, [r0], r
[all...] |
| vp9_idct16x16_1_add_neon.asm | 52 vld1.64 {d2}, [r1], r0
53 vld1.64 {d3}, [r1], r2
54 vld1.64 {d4}, [r1], r0
55 vld1.64 {d5}, [r1], r2
56 vld1.64 {d6}, [r1], r0
57 vld1.64 {d7}, [r1], r2
58 vld1.64 {d16}, [r1], r0
59 vld1.64 {d17}, [r1], r2
88 vld1.64 {d2}, [r1], r0
89 vld1.64 {d3}, [r1], r
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_intra_pred_luma_mode_18_34.s | 133 vld1.8 {d0},[r8],r6
135 vld1.8 {d1},[r8],r6
137 vld1.8 {d2},[r8],r6
138 vld1.8 {d3},[r8],r6
140 vld1.8 {d4},[r8],r6
141 vld1.8 {d5},[r8],r6
142 vld1.8 {d6},[r8],r6
144 vld1.8 {d7},[r8],r6
164 vld1.8 {d0},[r8],r6
168 vld1.8 {d1},[r8],r
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| 2013-10-11-select-stalls.ll | 3 ; Evaluate the two vld1.8 instructions in separate MBB's,
6 ; Update: After if-conversion the two vld1.8 instructions are in the same MBB
13 %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %foo, i32 1)
14 %vld2 = call <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* %bar, i32 1)
17 %retv = select i1 %tobool, <16 x i8> %vld1, <16 x i8> %vld2
21 declare <16 x i8> @llvm.arm.neon.vld1.v16i8.p0i8(i8* , i32 )
|
| vld1.ll | 9 ;CHECK: vld1.8 {d16}, [r0:64]
10 %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %A, i32 16)
16 ;CHECK: vld1.16
18 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1)
25 ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
28 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1)
36 ;CHECK: vld1.32
38 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1)
45 ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
48 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1
[all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| neont-VLD-reencoding.txt | 12 # CHECK: vld1.8 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x00]
13 # CHECK: vld1.8 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x00]
14 # CHECK: vld1.8 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x00]
15 # CHECK: vld1.8 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0x60,0x00]
16 # CHECK: vld1.8 {d0[4]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x00]
17 # CHECK: vld1.8 {d0[5]}, [r0], r0 @ encoding: [0xa0,0xf9,0xa0,0x00]
18 # CHECK: vld1.8 {d0[6]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x00]
19 # CHECK: vld1.8 {d0[7]}, [r0], r0 @ encoding: [0xa0,0xf9,0xe0,0x00]
30 # CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04]
31 # CHECK: vld1.16 {d0[0]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x10,0x04
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| omxVCM4P10_PredictIntra_16x16_s.S | 57 VLD1.8 {d0,d1},[r1]
85 VLD1.8 {d2[],d3[]},[r0],r4
86 VLD1.8 {d0[],d1[]},[r8],r4
90 VLD1.8 {d2[],d3[]},[r0],r4
91 VLD1.8 {d0[],d1[]},[r8],r4
94 VLD1.8 {d2[],d3[]},[r0],r4
95 VLD1.8 {d0[],d1[]},[r8],r4
98 VLD1.8 {d2[],d3[]},[r0],r4
99 VLD1.8 {d0[],d1[]},[r8],r4
112 VLD1.8 {d2[0]},[r0],r1
[all...] |
| armVCM4P10_Interpolate_Chroma_s.S | 53 VLD1.8 {d0},[r0],r10
56 VLD1.8 {d1},[r0],lr
67 VLD1.8 {d2},[r0],r10
69 VLD1.8 {d3},[r0],lr
71 VLD1.8 {d16},[r0],r10
73 VLD1.8 {d17},[r0],lr
76 VLD1.8 {d18},[r0],r10
80 VLD1.8 {d19},[r0],lr
82 VLD1.8 {d0},[r0],r10
86 VLD1.8 {d1},[r0],l
[all...] |
| omxVCM4P10_PredictIntraChroma_8x8_s.S | 55 VLD1.8 {d1[0]},[r0],r10
56 VLD1.8 {d1[1]},[r9],r10
57 VLD1.8 {d1[2]},[r0],r10
58 VLD1.8 {d1[3]},[r9],r10
59 VLD1.8 {d1[4]},[r0],r10
60 VLD1.8 {d1[5]},[r9],r10
61 VLD1.8 {d1[6]},[r0],r10
62 VLD1.8 {d1[7]},[r9]
65 VLD1.8 {d0},[r1]
106 VLD1.8 {d0},[r1
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vpx_scale/arm/neon/ |
| vp8_vpxyv12_copysrcframe_func_neon.asm | 53 vld1.8 {q0, q1}, [r2]!
54 vld1.8 {q4, q5}, [r10]!
55 vld1.8 {q2, q3}, [r2]!
56 vld1.8 {q6, q7}, [r10]!
57 vld1.8 {q8, q9}, [r2]!
58 vld1.8 {q12, q13}, [r10]!
59 vld1.8 {q10, q11}, [r2]!
60 vld1.8 {q14, q15}, [r10]!
77 vld1.8 {d0}, [r2]!
78 vld1.8 {d1}, [r10]
[all...] |
