| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 278 case ARM::VLDRD:
374 return isi32Load(Opc) || Opc == ARM::VLDRS || Opc == ARM::VLDRD;
410 case ARM::VLDRD:
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| Thumb1FrameLowering.cpp | 345 // Unwind MBBI to point to first LDR / VLDRD.
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| ARMBaseRegisterInfo.cpp | 496 case ARM::VLDRS: case ARM::VLDRD:
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| ARMScheduleSwift.td | 662 def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDRD$", "VLDRS$")>;
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| ARMBaseInstrInfo.cpp | [all...] |
| ARMFrameLowering.cpp | 725 // Unwind MBBI to point to first LDR / VLDRD.
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| ARMInstrVFP.td | 89 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
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| ARMFastISel.cpp | 499 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
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| ARMConstantIslandPass.cpp | [all...] |
| /art/compiler/utils/arm/ |
| assembler_arm32.h | 168 void vldrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
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| assembler_arm32.cc | 1062 void Arm32Assembler::vldrd(DRegister dd, const Address& ad, Condition cond) { function in class:art::arm::Arm32Assembler
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| assembler_thumb2.h | 213 void vldrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
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| assembler_arm.h | 634 virtual void vldrd(DRegister dd, const Address& ad, Condition cond = AL) = 0;
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| assembler_thumb2.cc | 2971 void Thumb2Assembler::vldrd(DRegister dd, const Address& ad, Condition cond) { function in class:art::arm::Thumb2Assembler
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