| /external/llvm/test/CodeGen/PowerPC/ |
| swaps-le-2.ll | 10 ; vector short vsr;
22 ; vsr = (vector short){vs[6], vs[6], vs[6], vs[6],
35 @vsr = common global <8 x i16> zeroinitializer, align 16
52 store <8 x i16> %vecinit14, <8 x i16>* @vsr, align 16
|
| /external/libexif/libexif/fuji/ |
| mnote-fuji-entry.c | 197 ExifSRational vsr; local
291 vsr = exif_get_srational (entry->data, entry->order);
292 if (!vsr.denominator) break;
293 snprintf (val, maxlen, "%2.4f", (double) vsr.numerator /
294 vsr.denominator);
|
| /external/clang/test/CodeGen/ |
| builtins-ppc-altivec.c | [all...] |
| /external/valgrind/VEX/pub/ |
| libvex_guest_ppc32.h | 95 // using a 64x128-bit vector. These are referred to as VSR[0..63].
97 // of VSR[0..31]. The 32x128-bit vector registers defined by the "Vector
98 // Facility [Category: Vector]" are now mapped to VSR[32..63].
|
| libvex_guest_ppc64.h | 133 // using a 64x128-bit vector. These are referred to as VSR[0..63].
135 // of VSR[0..31]. The 32x128-bit vector registers defined by the "Vector
136 // Facility [Category: Vector]" are now mapped to VSR[32..63].
|
| /external/v8/src/ppc/ |
| constants-ppc.h | 187 MFVSRD = 51 << 1, // Move From VSR Doubleword
197 MFVSRWZ = 115 << 1, // Move From VSR Word And Zero
204 MTVSRD = 179 << 1, // Move To VSR Doubleword
217 MTVSRWA = 211 << 1, // Move To VSR Word Algebraic
221 MTVSRWZ = 243 << 1, // Move To VSR Word And Zero
|
| /external/valgrind/none/tests/ppc32/ |
| jm-vmx.stdout.exp | [all...] |
| jm-vmx.stdout.exp_Minus_nan | [all...] |
| jm-insns.c | [all...] |
| /external/valgrind/none/tests/ppc64/ |
| jm-vmx.stdout.exp | [all...] |
| jm-vmx.stdout.exp-LE | [all...] |
| jm-vmx.stdout.exp_Minus_nan | [all...] |
| /external/libexif/libexif/olympus/ |
| mnote-olympus-entry.c | 280 ExifSRational vsr; local
805 vsr = exif_get_srational (entry->data, entry->order);
806 if (!vsr.denominator) {
809 r = R2D(vsr);
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/ |
| altivec.s | 177 vsr 2,9,28
|
| altivec.d | 182 2b0: (10 49 e2 c4|c4 e2 49 10) vsr v2,v9,v28
|
| /external/valgrind/memcheck/ |
| mc_machine.c | 197 // using a 64x128-bit vector. These are referred to as VSR[0..63].
199 // of VSR[0..31]. The 32x128-bit vector registers defined by the "Vector
200 // Facility [Category: Vector]" are now mapped to VSR[32..63].
397 // using a 64x128-bit vector. These are referred to as VSR[0..63].
399 // of VSR[0..31]. The 32x128-bit vector registers defined by the "Vector
400 // Facility [Category: Vector]" are now mapped to VSR[32..63].
[all...] |
| /external/llvm/test/MC/PowerPC/ |
| ppc64-encoding-vmx.s | 204 # CHECK-BE: vsr 2, 3, 4 # encoding: [0x10,0x43,0x22,0xc4]
205 # CHECK-LE: vsr 2, 3, 4 # encoding: [0xc4,0x22,0x43,0x10]
206 vsr 2, 3, 4
[all...] |
| vsx.s | [all...] |
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| ppc64-encoding-vmx.txt | 177 # CHECK: vsr 2, 3, 4
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrAltivec.td | [all...] |
| PPCVSXSwapRemoval.cpp | 496 case PPC::VSR:
[all...] |
| PPCInstrVSX.td | [all...] |
| /external/llvm/include/llvm/IR/ |
| IntrinsicsPowerPC.td | 582 def int_ppc_altivec_vsr : PowerPC_Vec_WWW_Intrinsic<"vsr">;
[all...] |
| /external/valgrind/VEX/switchback/ |
| test_ppc_jm1.c | [all...] |
| /external/valgrind/VEX/priv/ |
| host_ppc_defs.c | 627 case Pav_SHR: return "vsr"; // ' ',b,h,w,dw
[all...] |
