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Lines Matching refs:MmioOr32

245   MmioOr32 (MMCHS_SYSCTL, CEN);

269   MmioOr32 (CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1));

382       MmioOr32 (MMCHS_SYSCTL, SRC);

440       MmioOr32 (MMCHS_CAPA, (VS30 | VS18));

443       MmioOr32 (MMCHS_SYSCONFIG, ENAWAKEUP);

444       MmioOr32 (MMCHS_HCTL, IWE);

447       MmioOr32 (MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF));

452       MmioOr32 (MMCHS_SYSCTL, ICE);

458       MmioOr32 (MMCHS_HCTL, (SDBP_ON));

468       MmioOr32 (MMCHS_CON, INIT);

476       MmioOr32 (MMCHS_STAT, CC);

485       MmioOr32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_ON));

490       MmioOr32 (MMCHS_CON, OD);

510             MmioOr32 (MMCHS_HCTL, DTW_4_BIT);

584       MmioOr32 (MMCHS_STAT, BRR);

624       MmioOr32 (MMCHS_STAT, BWR);