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Lines Matching refs:MemoryTable

42   ARM_MEMORY_REGION_DESCRIPTOR  MemoryTable[5];

53   MemoryTable[0].PhysicalBase = MemoryBase;

54   MemoryTable[0].VirtualBase  = MemoryBase;

55   MemoryTable[0].Length       = MemoryLength;

56   MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;

59   MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;

60   MemoryTable[1].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;

61   MemoryTable[1].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;

62   MemoryTable[1].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;

65   MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;

66   MemoryTable[2].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;

67   MemoryTable[2].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;

68   MemoryTable[2].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;

71   MemoryTable[3].PhysicalBase = 0;

72   MemoryTable[3].VirtualBase  = 0;

73   MemoryTable[3].Length       = 0;

74   MemoryTable[3].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;

76   ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);