Lines Matching refs:UL
44 #define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
48 #define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
52 #define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
56 #define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
60 #define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
64 #define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
68 #define CM_CLKEN_ENABLE (7UL << 0)
76 #define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
80 #define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
84 #define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
88 #define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
91 #define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
95 #define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
98 #define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
102 #define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
105 #define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
108 #define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
111 #define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
114 #define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
117 #define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
120 #define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
123 #define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
127 #define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
130 #define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
133 #define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
136 #define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
139 #define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
142 #define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
145 #define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
148 #define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
152 #define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
155 #define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
