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Lines Matching refs:MmioOr32

105   MmioOr32 (MMCHS_SYSCTL, CEN);

150       MmioOr32 (MMCHS_SYSCTL, SRC);

364   MmioOr32 (CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1));

394   MmioOr32 (MMCHS_CON, INIT);

402   MmioOr32 (MMCHS_STAT, CC);

411   MmioOr32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_ON));

416   MmioOr32 (MMCHS_CON, OD);

438   MmioOr32 (MMCHS_SYSCTL, SRC);

459   MmioOr32 (MMCHS_SYSCTL, SRC);

562   MmioOr32 (MMCHS_HCTL, SDVS_3_0_V);

627         MmioOr32 (MMCHS_HCTL, DTW_4_BIT);

671       MmioOr32 (MMCHS_STAT, BRR);

713       MmioOr32 (MMCHS_STAT, BWR);

893         MmioOr32 (MMCHS_SYSCTL, SRD);

987         MmioOr32 (MMCHS_SYSCTL, SRD);

1057   MmioOr32 (MMCHS_CAPA, (VS30 | VS18));

1060   MmioOr32 (MMCHS_SYSCONFIG, ENAWAKEUP);

1061   MmioOr32 (MMCHS_HCTL, IWE);

1064   MmioOr32 (MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF));

1069   MmioOr32 (MMCHS_SYSCTL, ICE);

1075   MmioOr32 (MMCHS_HCTL, (SDBP_ON));