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81 #define B_PCH_LPC_COMMAND_MWIE                    BIT4  // Memory Write and Invalidate Enable

97 #define B_PCH_LPC_DEV_STS_CAP_LIST BIT4 // Capabilities List
373 #define B_PCH_ILB_DXXIR_IBR_MASK (BIT6 | BIT5 | BIT4) // INTB Mask
375 #define V_PCH_ILB_DXXIR_IBR_PIRQB BIT4 // INTB Mapping to IRQ B
377 #define V_PCH_ILB_DXXIR_IBR_PIRQD (BIT5 | BIT4) // INTB Mapping to IRQ D
379 #define V_PCH_ILB_DXXIR_IBR_PIRQF (BIT6 | BIT4) // INTB Mapping to IRQ F
381 #define V_PCH_ILB_DXXIR_IBR_PIRQH (BIT6 | BIT5 | BIT4) // INTB Mapping to IRQ H
415 #define B_PCH_ILB_RTCC_RTCB2 BIT4 // RTC Bias Resistor 2, Adds 120 Kohm
430 #define B_PCH_ILB_DEF1_FOAR BIT4 // 8254 Freeze_On_AnyRead
442 #define B_PCH_ILB_GNMI_NMIN BIT4 // NMI NOW
456 #define B_PCH_ILB_IRQE_IRQ4TO7EN (BIT7 | BIT6 | BIT5 | BIT4) // IRQ4 - IRQ7 Enable
471 #define B_PCH_ACPI_PM1_STS_WAK_PCIE3 BIT4 // PCI Express 3 Wake Status
489 #define B_PCH_ACPI_PM1_WAK_DIS_PCIE3 BIT4 // PCI Express 3 Disable
526 #define B_PCH_ACPI_GPE0a_STS_PUNIT_SCI BIT4 // PUNIT SCI Status
562 #define B_PCH_SMI_EN_ON_SLP_EN BIT4 // SMI On Sleep Enable
598 #define B_PCH_SMI_STS_ON_SLP_EN BIT4 // SMI On Sleep Enable Status
673 #define B_PCH_PMC_PRSTS_HOST_WAKE_STS BIT4 // PMC Host Wake Status
677 #define B_PCH_PMC_PM_CFG_NO_REBOOT BIT4 // No Reboot Strap
717 #define B_PCH_PMC_GEN_PMCON_SLP_S4_MAW (BIT5 | BIT4) // SLP_S4# Minimum Assertion Width
730 #define B_PCH_PMC_GEN_PMCON_SMI_LOCK BIT4 // SMI Lock
774 #define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC4 BIT4 // LPSS1 HS-UART #2 Disable
797 #define B_PCH_PMC_GPI_ROUT_2 (BIT5 | BIT4)
866 #define B_PCH_PMC_PSS_PG_STS_PCIE BIT4 // PCIe
896 #define B_PCH_PMC_D3_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4
933 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4
1027 #define B_PCH_NMI_SC_REF_TOGGLE BIT4 // Refresh Cycle toggle Status
1061 #define B_PCH_RTC_REGISTERA_DV (BIT6 | BIT5 | BIT4) // Division Chain Select
1090 #define B_PCH_RTC_REGISTERB_UIE BIT4 // Update-ended Interrupt Enable
1100 #define B_PCH_RTC_REGISTERC_UF BIT4 // Update-ended Flag
1202 #define B_PCH_PCH_HPET_TXC_PIC BIT4 // Periodic Interrupt Capable