Lines Matching refs:MODE
174 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
177 surflevel->mode = RADEON_SURF_MODE_1D;
284 surf->level[i].mode = RADEON_SURF_MODE_LINEAR;
312 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
345 surf->level[i].mode = RADEON_SURF_MODE_1D;
385 surf->level[i].mode = RADEON_SURF_MODE_2D;
387 if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
402 unsigned mode;
405 /* MSAA surfaces support the 2D mode only. */
407 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
408 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
411 /* tiling mode */
412 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
416 switch (mode) {
421 mode = RADEON_SURF_MODE_1D;
422 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
423 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
429 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
434 mode = RADEON_SURF_MODE_1D;
435 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
436 surf->flags |= RADEON_SURF_SET(mode, MODE);
449 /* check tiling mode */
450 switch (mode) {
583 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
586 surflevel->mode = RADEON_SURF_MODE_1D;
636 level[i].mode = RADEON_SURF_MODE_1D;
686 level[i].mode = RADEON_SURF_MODE_2D;
688 if (level[i].mode == RADEON_SURF_MODE_1D) {
702 unsigned mode)
717 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
722 mode = RADEON_SURF_MODE_1D;
723 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
724 surf->flags |= RADEON_SURF_SET(mode, MODE);
728 if (mode == RADEON_SURF_MODE_2D) {
831 unsigned mode;
834 /* MSAA surfaces support the 2D mode only. */
836 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
837 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
840 /* tiling mode */
841 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
845 switch (mode) {
850 mode = RADEON_SURF_MODE_1D;
851 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
852 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
857 r = eg_surface_sanity(surf_man, surf, mode);
865 /* check tiling mode */
866 switch (mode) {
906 unsigned mode, tileb, h_over_w;
909 /* tiling mode */
910 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
927 r = eg_surface_sanity(surf_man, surf, mode);
932 if (mode != RADEON_SURF_MODE_2D) {
1281 unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode)
1296 if (mode > RADEON_SURF_MODE_1D &&
1302 mode = RADEON_SURF_MODE_1D;
1303 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1304 surf->flags |= RADEON_SURF_SET(mode, MODE);
1307 if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) {
1320 switch (mode) {
1339 /* retrieve tiling mode value */
1390 /* retrieve tiling mode value */
1447 else if (surflevel->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
1488 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
1491 surflevel->mode = RADEON_SURF_MODE_1D;
1529 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1572 level[i].mode = RADEON_SURF_MODE_1D;
1654 level[i].mode = RADEON_SURF_MODE_2D;
1656 if (level[i].mode == RADEON_SURF_MODE_1D) {
1702 /* retrieve tiling mode value */
1721 unsigned mode, tile_mode, stencil_tile_mode;
1724 /* MSAA surfaces support the 2D mode only. */
1726 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1727 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
1730 /* tiling mode */
1731 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
1735 switch (mode) {
1740 mode = RADEON_SURF_MODE_1D;
1741 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1742 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
1747 r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
1755 /* check tiling mode */
1756 switch (mode) {
1781 unsigned mode, tile_mode, stencil_tile_mode;
1783 /* tiling mode */
1784 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
1789 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1790 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
1793 return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2111 unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode)
2124 if (mode > RADEON_SURF_MODE_1D &&
2130 mode = RADEON_SURF_MODE_1D;
2131 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2132 surf->flags |= RADEON_SURF_SET(mode, MODE);
2135 if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) {
2148 switch (mode) {
2180 /* retrieve tiling mode values */
2256 level[i].mode = RADEON_SURF_MODE_2D;
2258 if (level[i].mode == RADEON_SURF_MODE_1D) {
2325 unsigned mode, tile_mode, stencil_tile_mode;
2328 /* MSAA surfaces support the 2D mode only. */
2330 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2331 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
2334 /* tiling mode */
2335 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
2339 switch (mode) {
2344 mode = RADEON_SURF_MODE_1D;
2345 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2346 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
2351 r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2359 /* check tiling mode */
2360 switch (mode) {
2385 unsigned mode, tile_mode, stencil_tile_mode;
2387 /* tiling mode */
2388 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
2393 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2394 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
2397 return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2462 unsigned mode)
2530 unsigned mode, type;
2534 mode = RADEON_SURF_GET(surf->flags, MODE);
2536 r = radeon_surface_sanity(surf_man, surf, type, mode);
2547 unsigned mode, type;
2551 mode = RADEON_SURF_GET(surf->flags, MODE);
2553 r = radeon_surface_sanity(surf_man, surf, type, mode);
