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Lines Matching refs:RoundWidth

521         unsigned RoundWidth = 1 << Log2_32(StWidth);
522         assert(RoundWidth < StWidth);
523         unsigned ExtraWidth = StWidth - RoundWidth;
524         assert(ExtraWidth < RoundWidth);
525         assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
527         EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
534           // Store the bottom RoundWidth bits.
541           IncrementSize = RoundWidth / 8;
547               DAG.getConstant(RoundWidth, dl,
556           // Store the top RoundWidth bits.
566           IncrementSize = RoundWidth / 8;
731     unsigned RoundWidth = 1 << Log2_32(SrcWidth);
732     assert(RoundWidth < SrcWidth);
733     unsigned ExtraWidth = SrcWidth - RoundWidth;
734     assert(ExtraWidth < RoundWidth);
735     assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
737     EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
745       // Load the bottom RoundWidth bits.
752       IncrementSize = RoundWidth / 8;
769           DAG.getConstant(RoundWidth, dl,
777       // Load the top RoundWidth bits.
783       IncrementSize = RoundWidth / 8;