Lines Matching refs:Op
54 SDValue LegalizeOp(SDValue Op);
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
60 SDValue UnrollVSETCC(SDValue Op);
66 SDValue Expand(SDValue Op);
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
76 SDValue ExpandSEXTINREG(SDValue Op);
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
99 SDValue ExpandBSWAP(SDValue Op);
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
108 SDValue ExpandBITREVERSE(SDValue Op);
109 SDValue ExpandCTLZ_CTTZ_ZERO_UNDEF(SDValue Op);
115 SDValue Promote(SDValue Op);
120 SDValue PromoteINT_TO_FP(SDValue Op);
126 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
179 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
181 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
182 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
183 return Result.getValue(Op.getResNo());
186 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
189 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
192 SDNode* Node = Op.getNode();
196 for (const SDValue &Op : Node->op_values())
197 Ops.push_back(LegalizeOp(Op));
199 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
202 if (Op.getOpcode() == ISD::LOAD) {
203 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
210 return TranslateLegalizeResults(Op, Result);
214 return TranslateLegalizeResults(Op, Lowered);
216 if (Lowered->getNumValues() != Op->getNumValues()) {
224 return TranslateLegalizeResults(Op, Lowered);
228 return LegalizeOp(ExpandLoad(Op));
230 } else if (Op.getOpcode() == ISD::STORE) {
231 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
238 return TranslateLegalizeResults(Op, Result);
242 return TranslateLegalizeResults(Op, Lowered);
246 return LegalizeOp(ExpandStore(Op));
248 } else if (Op.getOpcode() == ISD::MSCATTER || Op.getOpcode() == ISD::MSTORE)
256 return TranslateLegalizeResults(Op, Result);
259 switch (Op.getOpcode()) {
261 return TranslateLegalizeResults(Op, Result);
355 Result = Promote(Op);
361 if (SDValue Tmp1 = TLI.LowerOperation(Op, DAG)) {
368 Result = Expand(Op);
372 if (Result != Op) {
379 AddLegalizedOperand(Op, Result);
383 SDValue VectorLegalizer::Promote(SDValue Op) {
386 switch (Op.getOpcode()) {
390 return PromoteINT_TO_FP(Op);
394 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
402 MVT VT = Op.getSimpleValueType();
403 assert(Op.getNode()->getNumValues() == 1 &&
405 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
406 SDLoc dl(Op);
407 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
409 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
410 if (Op.getOperand(j).getValueType().isVector())
411 if (Op.getOperand(j)
416 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
418 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
420 Operands[j] = Op.getOperand(j);
423 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
427 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
429 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
432 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
435 EVT VT = Op.getOperand(0).getValueType();
436 assert(Op.getNode()->getNumValues() == 1 &&
449 SDLoc dl(Op);
450 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
452 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
454 for (unsigned j = 0; j != Op
455 if (Op.getOperand(j).getValueType().isVector())
456 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
458 Operands[j] = Op.getOperand(j);
461 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
468 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
469 assert(Op.getNode()->getNumValues() == 1 &&
471 EVT VT = Op.getValueType();
488 SDLoc loc(Op);
489 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
490 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
494 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
495 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
505 SDLoc dl(Op);
603 default: llvm_unreachable("Unknown extended-load op!");
624 Op.getNode()->getValueType(0), Vals);
632 AddLegalizedOperand(Op.getValue(0), Value);
633 AddLegalizedOperand(Op.getValue(1), NewChain);
635 return (Op.getResNo() ? NewChain : Value);
638 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
639 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
663 = DAG.getTruncStore(ST->getChain(), SDLoc(Op), ST->getValue(),
673 AddLegalizedOperand(Op, TF);
677 SDValue VectorLegalizer::Expand(SDValue Op) {
678 switch (Op->getOpcode()) {
680 return ExpandSEXTINREG(Op);
682 return ExpandANY_EXTEND_VECTOR_INREG(Op);
684 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
686 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
688 return ExpandBSWAP(Op);
690 return ExpandVSELECT(Op);
692 return ExpandSELECT(Op);
694 return ExpandUINT_TO_FLOAT(Op);
696 return ExpandFNEG(Op);
698 return UnrollVSETCC(Op);
700 return ExpandBITREVERSE(Op);
703 return ExpandCTLZ_CTTZ_ZERO_UNDEF(Op);
705 return DAG.UnrollVectorOp(Op.getNode());
709 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
713 EVT VT = Op.getValueType();
714 SDLoc DL(Op);
716 SDValue Mask = Op.getOperand(0);
717 SDValue Op1 = Op.getOperand(1);
718 SDValue Op2 = Op.getOperand(2);
726 // AND,OR,XOR, we will have to scalarize the op.
734 return DAG.UnrollVectorOp(Op.getNode());
764 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
767 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
768 EVT VT = Op.getValueType();
773 return DAG.UnrollVectorOp(Op.getNode());
775 SDLoc DL(Op);
776 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
782 Op = Op.getOperand(0);
783 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
784 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
789 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
790 SDLoc DL(Op);
791 EVT VT = Op.getValueType();
793 SDValue Src = Op.getOperand(0);
812 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
813 SDLoc DL(Op);
814 EVT VT = Op.getValueType();
815 SDValue Src = Op.getOperand(0);
820 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
829 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
836 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
837 SDLoc DL(Op);
838 EVT VT = Op.getValueType();
840 SDValue Src = Op.getOperand(0);
870 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
871 EVT VT = Op.getValueType();
880 return DAG.UnrollVectorOp(Op.getNode());
882 SDLoc DL(Op);
883 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
884 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT), ShuffleMask);
885 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
888 SDValue VectorLegalizer::ExpandBITREVERSE(SDValue Op) {
889 EVT VT = Op.getValueType();
893 return DAG.UnrollVectorOp(Op.getNode());
910 SDLoc DL(Op);
911 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
912 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
914 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op);
915 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
925 return DAG.UnrollVectorOp(Op.getNode());
928 return Op;
931 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
934 SDLoc DL(Op);
936 SDValue Mask = Op.getOperand(0);
937 SDValue Op1 = Op.getOperand(1);
938 SDValue Op2 = Op.getOperand(2);
943 // AND,OR,XOR, we will have to scalarize the op.
954 return DAG.UnrollVectorOp(Op.getNode());
956 // If the mask and the type are different sizes, unroll the vector op. This
960 return DAG.UnrollVectorOp(Op.getNode());
975 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
978 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
979 EVT VT = Op.getOperand(0).getValueType();
980 SDLoc DL(Op);
985 return DAG.UnrollVectorOp(Op.getNode());
1001 SDValue TWOHW = DAG.getConstantFP(1 << (BW/2), DL, Op.getValueType());
1004 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
1005 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
1010 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
1011 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
1012 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
1015 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1019 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
1020 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1021 SDLoc DL(Op);
1022 SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
1024 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
1025 Zero, Op.getOperand(0));
1027 return DAG.UnrollVectorOp(Op.getNode());
1030 SDValue VectorLegalizer::ExpandCTLZ_CTTZ_ZERO_UNDEF(SDValue Op) {
1032 unsigned Opc = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF ? ISD::CTLZ : ISD::CTTZ;
1033 if (TLI.isOperationLegalOrCustom(Opc, Op.getValueType())) {
1034 SDLoc DL(Op);
1035 return DAG.getNode(Opc, DL, Op.getValueType(), Op.getOperand(0));
1039 return DAG.UnrollVectorOp(Op.getNode());
1042 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
1043 EVT VT = Op.getValueType();
1046 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
1048 SDLoc dl(Op);
