Lines Matching refs:ADD
321 // a got and then add the offset.
325 // If the code is position independent we will have to add a base register.
1075 // None of the shifted in bits are needed. Add a truncate of the
1134 case ISD::ADD:
1137 // Add, Sub, and Mul don't demand any bits in positions beyond that
1553 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2008 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2034 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2100 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2192 if (N->getOpcode() == ISD::ADD) {
2274 /// If it is invalid, don't add anything to Ops.
2300 // If we have "(add GV, C)", pull out GV/C
2301 if (Op.getOpcode() == ISD::ADD) {
2864 // If d > 0 and m < 0, add the numerator
2866 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2882 // Extract the sign bit and add it to the quotient
2888 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2956 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3067 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
3068 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
3076 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
3077 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
3176 BasePTR = DAG.getNode(ISD::ADD, SL, PtrVT, BasePTR,
3227 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
3307 Ptr = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr, PtrIncrement);
3308 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtrVT, StackPtr,
3366 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
3378 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
3469 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtrVT,
3471 Ptr = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr, PtrIncrement);
3520 Ptr = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
