Lines Matching defs:CC
1049 /// CC
1050 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
1051 switch (CC) {
1077 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1078 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1082 switch (CC) {
1138 /// Convert a DAG fp condition code to an AArch64 CC.
1141 static void changeFPCCToANDAArch64CC(ISD::CondCode CC,
1145 switch (CC) {
1147 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1168 /// CC usable with the vector instructions. Fewer operations are available
1171 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1176 switch (CC) {
1179 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1195 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1205 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1226 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1240 !isUnsignedIntSetCC(CC)) {
1286 /// ccmp D, inv(CD), CC
1296 ISD::CondCode CC, SDValue CCOp,
1310 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1398 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
1401 CC = getSetCCInverse(CC, isInteger);
1405 OutCC = changeIntCCToAArch64CC(CC);
1409 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC);
1415 ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
1417 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate,
1426 return emitComparison(LHS, RHS, CC, DL, DAG);
1428 return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL,
1505 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1513 switch (CC) {
1522 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1532 CC = (CC
1543 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1554 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1564 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1594 CC, dl, DAG);
1595 AArch64CC = changeIntCCToAArch64CC(CC);
1601 if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
1608 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1609 AArch64CC = changeIntCCToAArch64CC(CC);
1616 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1629 CC = AArch64CC::VS;
1633 CC = AArch64CC::HS;
1637 CC = AArch64CC::VS;
1641 CC = AArch64CC::LO;
1646 CC = AArch64CC::NE;
1747 // (xor x, (select_cc a, b, cc, 0, -1) )
1749 // (csel x, (xor x, -1), cc ...)
1753 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1776 CC = ISD::getSetCCInverse(CC, true);
1782 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1837 AArch64CC::CondCode CC;
1840 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1849 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
2418 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2420 switch (CC) {
3614 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3624 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3630 CC = ISD::SETNE;
3640 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3651 if (CC == ISD::SETNE)
3667 if (CC == ISD::SETEQ) {
3683 } else if (CC == ISD::SETNE) {
3699 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3708 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3719 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3726 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3728 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3730 changeFPCCToAArch64CC(CC, CC1, CC2);
3859 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3870 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3883 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3896 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3899 changeFPCCToAArch64CC(CC, CC1, CC2);
3901 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3909 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3912 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3924 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
3931 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3937 CC = ISD::SETNE;
3962 CC = ISD::getSetCCInverse(CC, true);
3966 CC = ISD::getSetCCInverse(CC, true);
3973 CC = ISD::getSetCCInverse(CC, true);
3981 CC = ISD::getSetCCInverse(CC, true);
4024 CCCC, true);
4035 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
4045 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
4047 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
4050 changeFPCCToAArch64CC(CC, CC1, CC2);
4055 // RHS. We're effectively OR'ing the two CC's together.
4067 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4073 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4103 ISD::CondCode CC;
4108 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
4112 CC = ISD::SETNE;
4114 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4719 if (StringRef("{cc}").equals_lower(Constraint))
6673 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6686 switch (CC) {
6725 switch (CC) {
6769 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6777 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6789 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6793 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
8232 ISD::CondCode CC;
8238 AArch64CC::CondCode CC;
8266 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8272 // - csel 1, 0, cc
8273 // - csel 0, 1, !cc
8280 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
8295 // Update the comparison when we are interested in !cc.
8297 SetCCInfo.Info.AArch64.CC =
8298 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
8312 // (add x, [zext] (setcc cc ...) )
8314 // (csel x, (add x, 1), !cc ...)
8342 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
8348 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
9128 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
9129 if ((Op == ISD::SMAX && CC != ISD::SETGT && CC != ISD::SETGE) ||
9130 (Op == ISD::UMAX && CC != ISD::SETUGT && CC != ISD::SETUGE) ||
9131 (Op == ISD::SMIN && CC != ISD::SETLT && CC != ISD::SETLE) ||
9132 (Op == ISD::UMIN && CC != ISD::SETULT && CC != ISD::SETULE) ||
9133 (Op == ISD::FMAXNUM && CC != ISD::SETOGT && CC != ISD::SETOGE &&
9134 CC != ISD::SETUGT && CC != ISD::SETUGE && CC != ISD::SETGT &&
9135 CC != ISD::SETGE) ||
9136 (Op == ISD::FMINNUM && CC != ISD::SETOLT && CC != ISD::SETOLE &&
9137 CC != ISD::SETULT && CC != ISD::SETULE && CC != ISD::SETLT &&
9138 CC != ISD::SETLE))
9382 // | Input | | AddConstant | | CompConstant| | CC |
9404 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
9438 static bool isEquivalentMaskless(unsigned CC, unsigned width,
9454 switch(CC) {
9519 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
9571 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
9600 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
9601 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
9633 if (CC == AArch64CC::EQ)
