Lines Matching refs:Op
136 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
1616 auto Op = make_unique<AArch64Operand>(k_Token, Ctx);
1617 Op->Tok.Data = Str.data();
1618 Op->Tok.Length = Str.size();
1619 Op->Tok.IsSuffix = IsSuffix;
1620 Op->StartLoc = S;
1621 Op->EndLoc = S;
1622 return Op;
1627 auto Op = make_unique<AArch64Operand>(k_Register, Ctx);
1628 Op->Reg.RegNum = RegNum;
1629 Op->Reg.isVector = isVector;
1630 Op->StartLoc = S;
1631 Op->EndLoc = E;
1632 return Op;
1638 auto Op = make_unique<AArch64Operand>(k_VectorList, Ctx);
1639 Op->VectorList.RegNum = RegNum;
1640 Op->VectorList.Count = Count;
1641 Op->VectorList.NumElements = NumElements;
1642 Op->VectorList.ElementKind = ElementKind;
1643 Op->StartLoc = S;
1644 Op->EndLoc = E;
1645 return Op;
1650 auto Op = make_unique<AArch64Operand>(k_VectorIndex, Ctx);
1651 Op->VectorIndex.Val = Idx;
1652 Op->StartLoc = S;
1653 Op->EndLoc = E;
1654 return Op;
1659 auto Op = make_unique<AArch64Operand>(k_Immediate, Ctx);
1660 Op->Imm.Val = Val;
1661 Op->StartLoc = S;
1662 Op->EndLoc = E;
1663 return Op;
1670 auto Op = make_unique<AArch64Operand>(k_ShiftedImm, Ctx);
1671 Op->ShiftedImm .Val = Val;
1672 Op->ShiftedImm.ShiftAmount = ShiftAmount;
1673 Op->StartLoc = S;
1674 Op->EndLoc = E;
1675 return Op;
1680 auto Op = make_unique<AArch64Operand>(k_CondCode, Ctx);
1681 Op->CondCode.Code = Code;
1682 Op->StartLoc = S;
1683 Op->EndLoc = E;
1684 return Op;
1689 auto Op = make_unique<AArch64Operand>(k_FPImm, Ctx);
1690 Op->FPImm.Val = Val;
1691 Op->StartLoc = S;
1692 Op->EndLoc = S;
1693 return Op;
1700 auto Op = make_unique<AArch64Operand>(k_Barrier, Ctx);
1701 Op->Barrier.Val = Val;
1702 Op->Barrier.Data = Str.data();
1703 Op->Barrier.Length = Str.size();
1704 Op->StartLoc = S;
1705 Op->EndLoc = S;
1706 return Op;
1714 auto Op = make_unique<AArch64Operand>(k_SysReg, Ctx);
1715 Op->SysReg.Data = Str.data();
1716 Op->SysReg.Length = Str.size();
1717 Op->SysReg.MRSReg = MRSReg;
1718 Op->SysReg.MSRReg = MSRReg;
1719 Op->SysReg.PStateField = PStateField;
1720 Op->StartLoc = S;
1721 Op->EndLoc = S;
1722 return Op;
1727 auto Op = make_unique<AArch64Operand>(k_SysCR, Ctx);
1728 Op->SysCRImm.Val = Val;
1729 Op->StartLoc = S;
1730 Op->EndLoc = E;
1731 return Op;
1738 auto Op = make_unique<AArch64Operand>(k_Prefetch, Ctx);
1739 Op->Prefetch.Val = Val;
1740 Op->Barrier.Data = Str.data();
1741 Op->Barrier.Length = Str.size();
1742 Op->StartLoc = S;
1743 Op->EndLoc = S;
1744 return Op;
1751 auto Op = make_unique<AArch64Operand>(k_PSBHint, Ctx);
1752 Op->PSBHint.Val = Val;
1753 Op->PSBHint.Data = Str.data();
1754 Op->PSBHint.Length = Str.size();
1755 Op->StartLoc = S;
1756 Op->EndLoc = S;
1757 return Op;
1763 auto Op = make_unique<AArch64Operand>(k_ShiftExtend, Ctx);
1764 Op->ShiftExtend.Type = ShOp;
1765 Op->ShiftExtend.Amount = Val;
1766 Op->ShiftExtend.HasExplicitAmount = HasExplicitAmount;
1767 Op->StartLoc = S;
1768 Op->EndLoc = E;
1769 return Op;
2462 StringRef Op = Tok.getString();
2482 if (!Op.compare_lower("ialluis")) {
2485 } else if (!Op.compare_lower("iallu")) {
2488 } else if (!Op.compare_lower("ivau")) {
2495 if (!Op.compare_lower("zva")) {
2498 } else if (!Op.compare_lower("ivac")) {
2501 } else if (!Op.compare_lower("isw")) {
2504 } else if (!Op.compare_lower("cvac")) {
2507 } else if (!Op.compare_lower("csw")) {
2510 } else if (!Op.compare_lower("cvau")) {
2513 } else if (!Op.compare_lower("civac")) {
2516 } else if (!Op.compare_lower("cisw")) {
2519 } else if (!Op.compare_lower("cvap")) {
2530 if (!Op.compare_lower("s1e1r")) {
2533 } else if (!Op.compare_lower("s1e2r")) {
2536 } else if (!Op.compare_lower("s1e3r")) {
2539 } else if (!Op.compare_lower("s1e1w")) {
2542 } else if (!Op.compare_lower("s1e2w")) {
2545 } else if (!Op.compare_lower("s1e3w")) {
2548 } else if (!Op.compare_lower("s1e0r")) {
2551 } else if (!Op.compare_lower("s1e0w")) {
2554 } else if (!Op.compare_lower("s12e1r")) {
2557 } else if (!Op.compare_lower("s12e1w")) {
2560 } else if (!Op.compare_lower("s12e0r")) {
2563 } else if (!Op.compare_lower("s12e0w")) {
2566 } else if (!Op.compare_lower("s1e1rp")) {
2573 } else if (!Op.compare_lower("s1e1wp")) {
2584 if (!Op.compare_lower("vmalle1is")) {
2587 } else if (!Op.compare_lower("alle2is")) {
2590 } else if (!Op.compare_lower("alle3is")) {
2593 } else if (!Op.compare_lower("vae1is")) {
2596 } else if (!Op.compare_lower("vae2is")) {
2599 } else if (!Op.compare_lower("vae3is")) {
2602 } else if (!Op.compare_lower("aside1is")) {
2605 } else if (!Op.compare_lower("vaae1is")) {
2608 } else if (!Op.compare_lower("alle1is")) {
2611 } else if (!Op.compare_lower("vale1is")) {
2614 } else if (!Op.compare_lower("vaale1is")) {
2617 } else if (!Op.compare_lower("vmalle1")) {
2620 } else if (!Op.compare_lower("alle2")) {
2623 } else if (!Op.compare_lower("vale2is")) {
2626 } else if (!Op.compare_lower("vale3is")) {
2629 } else if (!Op.compare_lower("alle3")) {
2632 } else if (!Op.compare_lower("vae1")) {
2635 } else if (!Op.compare_lower("vae2")) {
2638 } else if (!Op.compare_lower("vae3")) {
2641 } else if (!Op.compare_lower("aside1")) {
2644 } else if (!Op.compare_lower("vaae1")) {
2647 } else if (!Op.compare_lower("alle1")) {
2650 } else if (!Op.compare_lower("vale1")) {
2653 } else if (!Op.compare_lower("vale2")) {
2656 } else if (!Op.compare_lower("vale3")) {
2659 } else if (!Op.compare_lower("vaale1")) {
2662 } else if (!Op.compare_lower("ipas2e1")) {
2665 } else if (!Op.compare_lower("ipas2le1")) {
2668 } else if (!Op.compare_lower("ipas2e1is")) {
2671 } else if (!Op.compare_lower("ipas2le1is")) {
2674 } else if (!Op.compare_lower("vmalls12e1")) {
2677 } else if (!Op.compare_lower("vmalls12e1is")) {
2689 bool ExpectRegister = (Op.lower().find("all") == StringRef::npos);
2708 return TokError("specified " + Mnemonic + " op requires a register");
2711 return TokError("specified " + Mnemonic + " op does not use a register");
3249 // If the op is an imm and can be fit into a mov, then replace ldr with mov.
3744 AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[0]);
3745 assert(Op.isToken() && "Leading operand should always be a mnemonic!");
3747 StringRef Tok = Op.getToken();
3772 "ubfm", false, Op.getStartLoc(), getContext());
3822 "bfm", false, Op.getStartLoc(), getContext());
3885 "bfm", false, Op.getStartLoc(), getContext());
3888 "sbfm", false, Op.getStartLoc(), getContext());
3891 "ubfm", false, Op.getStartLoc(), getContext());
3939 "bfm", false, Op.getStartLoc(), getContext());
3942 "sbfm", false, Op.getStartLoc(), getContext());
3945 "ubfm", false, Op.getStartLoc(), getContext());
3958 AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[2]);
3959 if (Op.isReg()) {
3960 unsigned Reg = getXRegFromWReg(Op.getReg());
3961 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(),
3962 Op.getEndLoc(), getContext());
3967 AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[1]);
3968 if (Op.isReg() &&
3970 Op.getReg())) {
3973 AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[2]);
3974 if (Op.isReg()) {
3975 unsigned Reg = getXRegFromWReg(Op.getReg());
3976 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(),
3977 Op.getEndLoc(), getContext());
3983 AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[1]);
3984 if (Op.isReg() &&
3986 Op.getReg())) {
3989 AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[1]);
3990 if (Op.isReg()) {
3991 unsigned Reg = getWRegFromXReg(Op.getReg());
3992 Operands[1] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(),
3993 Op.getEndLoc(), getContext());
4008 Operands[2] = AArch64Operand::CreateReg(zreg, false, Op.getStartLoc(),
4009 Op.getEndLoc(), getContext());
4547 AArch64Operand &Op = static_cast<AArch64Operand &>(AsmOp);
4595 if (!Op.isImm())
4597 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
