Lines Matching refs:AMDGPUDAGToDAGISel
55 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
61 AMDGPUDAGToDAGISel(TargetMachine &TM);
62 virtual ~AMDGPUDAGToDAGISel();
164 return new AMDGPUDAGToDAGISel(TM);
167 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
170 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
175 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
178 bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
188 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
219 SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
261 void AMDGPUDAGToDAGISel::Select(SDNode *N) {
485 bool AMDGPUDAGToDAGISel::isConstantLoad(const MemSDNode *N, int CbId) const {
494 bool AMDGPUDAGToDAGISel::isUniformBr(const SDNode *N) const {
501 const char *AMDGPUDAGToDAGISel::getPassName() const {
509 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
519 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
529 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
558 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
578 void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
622 void AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
641 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
656 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
718 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
792 bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
868 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
896 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
906 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
937 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
965 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
972 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
980 bool AMDGPUDAGToDAGISel::SelectMUBUFConstant(SDValue Constant,
1024 bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicOffset(SDValue Offset,
1035 bool AMDGPUDAGToDAGISel::SelectMUBUFIntrinsicVOffset(SDValue Offset,
1069 bool AMDGPUDAGToDAGISel::SelectFlat(SDValue Addr,
1088 bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
1123 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
1142 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
1148 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
1161 bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
1168 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
1174 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
1186 bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
1193 bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
1217 SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, const SDLoc &DL,
1229 void AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
1254 void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
1330 void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
1364 void AMDGPUDAGToDAGISel::SelectATOMIC_CMP_SWAP(SDNode *N) {
1428 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1450 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src,
1456 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1467 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods0(SDValue In, SDValue &Src,
1477 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
1486 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
1494 void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
1550 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
