Lines Matching refs:Op
687 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
692 SDLoc(Op).getDebugLoc());
694 auto Ops = {DAG.getConstant(0, SDLoc(), Op.getValueType()), Op.getOperand(0)};
698 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
700 switch (Op.getOpcode()) {
702 Op->dump(&DAG);
706 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
707 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
708 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
709 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
710 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
711 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
712 case ISD::FREM: return LowerFREM(Op, DAG);
713 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
714 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
715 case ISD::FRINT: return LowerFRINT(Op, DAG);
716 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
717 case ISD::FROUND: return LowerFROUND(Op, DAG);
718 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
719 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
720 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
721 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
722 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
725 return LowerCTLZ(Op, DAG);
726 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
728 return Op;
845 SDValue Op,
849 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
883 return DAG.getConstant(Offset, SDLoc(Op),
890 Fn, "unsupported initializer for address space", SDLoc(Op).getDebugLoc());
895 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
899 for (const SDUse &U : Op->ops())
902 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
905 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
909 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
910 EVT VT = Op.getValueType();
911 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
914 return DAG.getBuildVector(Op.getValueType(), SDLoc(Op), Args);
917 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
919 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
920 SDLoc DL(Op);
921 EVT VT = Op.getValueType();
924 default: return Op;
927 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
930 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
931 Op.getOperand(2));
935 Op.getOperand(1),
936 Op.getOperand(2),
937 Op.getOperand(3));
941 Op.getOperand(1),
942 Op.getOperand(2),
943 Op.getOperand(3));
946 return DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(1));
1028 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1029 SDLoc SL(Op);
1031 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1042 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1043 SDLoc SL(Op);
1045 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1050 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1051 SDLoc SL(Op);
1053 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);
1058 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1060 LoadSDNode *Load = cast<LoadSDNode>(Op);
1061 EVT VT = Op.getValueType();
1072 SDLoc SL(Op);
1082 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1116 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1118 StoreSDNode *Store = cast<StoreSDNode>(Op);
1129 SDLoc DL(Op);
1174 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1176 StoreSDNode *Store = cast<StoreSDNode>(Op);
1188 SDLoc SL(Op);
1231 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
1233 SDLoc DL(Op);
1234 EVT VT = Op.getValueType();
1235 SDValue LHS = Op.getOperand(0);
1236 SDValue RHS = Op.getOperand(1);
1334 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1337 assert(Op.getValueType() == MVT::i64);
1339 SDLoc DL(Op);
1340 EVT VT = Op.getValueType();
1347 SDValue LHS = Op.getOperand(0);
1351 SDValue RHS = Op.getOperand(1);
1412 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1414 SDLoc DL(Op);
1415 EVT VT = Op.getValueType();
1419 LowerUDIVREM64(Op, DAG, Results);
1424 if (SDValue Res = LowerDIVREM24(Op, DAG, false))
1428 SDValue Num = Op.getOperand(0);
1429 SDValue Den = Op.getOperand(1);
1527 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1529 SDLoc DL(Op);
1530 EVT VT = Op.getValueType();
1532 SDValue LHS = Op.getOperand(0);
1533 SDValue RHS = Op.getOperand(1);
1539 if (SDValue Res = LowerDIVREM24(Op, DAG, true))
1588 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1589 SDLoc SL(Op);
1590 EVT VT = Op.getValueType();
1591 SDValue X = Op.getOperand(0);
1592 SDValue Y = Op.getOperand(1);
1603 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1604 SDLoc SL(Op);
1605 SDValue Src = Op.getOperand(0);
1643 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1644 SDLoc SL(Op);
1645 SDValue Src = Op.getOperand(0);
1647 assert(Op.getValueType() == MVT::f64);
1692 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1693 SDLoc SL(Op);
1694 SDValue Src = Op.getOperand(0);
1696 assert(Op.getValueType() == MVT::f64);
1719 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1723 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1727 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
1728 SDLoc SL(Op);
1729 SDValue X = Op.getOperand(0);
1755 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
1756 SDLoc SL(Op);
1757 SDValue X = Op.getOperand(0);
1812 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
1813 EVT VT = Op.getValueType();
1816 return LowerFROUND32(Op, DAG);
1819 return LowerFROUND64(Op, DAG);
1824 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1825 SDLoc SL(Op);
1826 SDValue Src = Op.getOperand(0);
1849 SDValue AMDGPUTargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
1850 SDLoc SL(Op);
1851 SDValue Src = Op.getOperand(0);
1852 bool ZeroUndef = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF;
1903 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
1924 SDLoc SL(Op);
1925 SDValue Src = Op.getOperand(0);
1988 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
1990 SDLoc SL(Op);
1991 SDValue Src = Op.getOperand(0);
2011 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2013 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2016 EVT DestVT = Op.getValueType();
2018 return LowerINT_TO_FP64(Op, DAG, false);
2021 return LowerINT_TO_FP32(Op, DAG, false);
2026 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2028 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2031 EVT DestVT = Op.getValueType();
2033 return LowerINT_TO_FP32(Op, DAG, true);
2036 return LowerINT_TO_FP64(Op, DAG, true);
2041 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2043 SDLoc SL(Op);
2045 SDValue Src = Op.getOperand(0);
2070 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2072 SDValue Src = Op.getOperand(0);
2074 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2075 return LowerFP64_TO_INT(Op, DAG, true);
2080 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2082 SDValue Src = Op.getOperand(0);
2084 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2085 return LowerFP64_TO_INT(Op, DAG, false);
2090 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2092 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2093 MVT VT = Op.getSimpleValueType();
2099 SDValue Src = Op.getOperand(0);
2100 SDLoc DL(Op);
2118 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2120 EVT VT = Op.getValueType();
2121 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2126 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2127 EVT VT = Op.getValueType();
2133 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2136 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2140 EVT VT = Op.getValueType();
2145 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2477 // Get FFBH node if the incoming op may have been type legalized from a smaller
2482 const SDLoc &SL, SDValue Op) {
2483 EVT VT = Op.getValueType();
2489 Op = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Op);
2491 SDValue FFBH = DAG.getNode(AMDGPUISD::FFBH_U32, SL, MVT::i32, Op);
2918 const SDValue Op,
2928 unsigned Opc = Op.getOpcode();
2941 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2957 SDValue Op,
2960 switch (Op.getOpcode()) {
2962 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2967 if (!isNullConstant(Op.getOperand(1)))
2971 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2976 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
