Lines Matching refs:SDValue
31 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
32 const SDValue &InitPtr,
33 SDValue Chain,
35 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
44 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
59 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
63 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
64 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
66 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
70 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
71 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
72 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
73 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
74 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
75 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
76 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
77 SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
78 SDValue RHS, DAGCombinerInfo &DCI) const;
79 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
84 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
88 std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
90 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
91 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
94 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
97 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
99 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
103 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
104 SmallVectorImpl<SDValue> &Results) const;
130 bool isZExtFree(SDValue Val, EVT VT2) const override;
152 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
154 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
156 SDValue LowerCall(CallLoweringInfo &CLI,
157 SmallVectorImpl<SDValue> &InVals) const override;
159 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
162 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
163 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
165 SmallVectorImpl<SDValue> &Results,
168 SDValue CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
169 SDValue RHS, SDValue True, SDValue False,
170 SDValue CC, DAGCombinerInfo &DCI) const;
174 SDValue getRsqrtEstimate(SDValue Operand,
178 SDValue getRecipEstimate(SDValue Operand,
188 void computeKnownBitsForTargetNode(const SDValue Op,
194 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
201 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
