Lines Matching refs:Op
490 auto Op = llvm::make_unique<AMDGPUOperand>(Immediate);
491 Op->Imm.Val = Val;
492 Op->Imm.IsFPImm = IsFPImm;
493 Op->Imm.Type = Type;
494 Op->Imm.Mods = {false, false, false};
495 Op->StartLoc = Loc;
496 Op->EndLoc = Loc;
497 return Op;
515 auto Op = llvm::make_unique<AMDGPUOperand>(Register);
516 Op->Reg.RegNo = RegNo;
517 Op->Reg.TRI = TRI;
518 Op->Reg.STI = STI;
519 Op->Reg.Mods = {false, false, false};
520 Op->Reg.IsForcedVOP3 = ForceVOP3;
521 Op->StartLoc = S;
522 Op->EndLoc = E;
523 return Op;
527 auto Op = llvm::make_unique<AMDGPUOperand>(Expression);
528 Op->Expr = Expr;
529 Op->StartLoc = S;
530 Op->EndLoc = S;
531 return Op;
644 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
1085 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
1086 Op.setModifiers(Mods);
1121 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
1122 Op.setModifiers(Mods);
1664 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1667 if (Op.isReg()) {
1668 Op.addRegOperands(Inst, 1);
1673 OptionalIdx[Op.getImmTy()] = i;
1689 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1692 if (Op.isReg()) {
1693 Op.addRegOperands(Inst, 1);
1697 if (Op.isToken() && Op.getToken() == "gds") {
1703 OptionalIdx[Op.getImmTy()] = i;
2133 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
2136 if (Op.isReg()) {
2137 Op.addRegOperands(Inst, 1);
2142 if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {
2143 Op.addImmOperands(Inst, 1);
2149 if (Op.isToken()) {
2152 assert(Op.isImm());
2155 OptionalIdx[Op.getImmTy()] = i;
2186 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2189 if (Op.isRegOrImm()) {
2190 Op.addRegOrImmOperands(Inst, 1);
2192 } else if (Op.isImmModifier()) {
2193 OptionalIdx[Op.getImmTy()] = I;
2222 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2225 if (Op.isRegOrImm()) {
2226 Op.addRegOrImmOperands(Inst, 1);
2228 } else if (Op.isImmModifier()) {
2229 OptionalIdx[Op.getImmTy()] = I;
2357 for (const OptionalOperand &Op : AMDGPUOptionalOperandTable) {
2359 if (Op.IsBit) {
2360 res = parseNamedBit(Op.Name, Operands, Op.Type);
2361 } else if (Op.Type == AMDGPUOperand::ImmTyOModSI) {
2363 } else if (Op.Type == AMDGPUOperand::ImmTySdwaDstSel ||
2364 Op.Type == AMDGPUOperand::ImmTySdwaSrc0Sel ||
2365 Op.Type == AMDGPUOperand::ImmTySdwaSrc1Sel) {
2366 res = parseSDWASel(Operands, Op.Name, Op.Type);
2367 } else if (Op.Type == AMDGPUOperand::ImmTySdwaDstUnused) {
2370 res = parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.ConvertResult);
2419 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2420 if (Op.isRegOrImmWithInputMods()) {
2422 Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
2423 } else if (Op.isImm()) {
2424 OptionalIdx[Op.getImmTy()] = I;
2594 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2596 if (Op.isRegOrImmWithInputMods()) {
2598 Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
2599 } else if (Op.isDPPCtrl()) {
2600 Op.addImmOperands(Inst, 1);
2601 } else if (Op.isImm()) {
2603 OptionalIdx[Op.getImmTy()] = I;
2701 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2704 Op.isReg() &&
2705 Op.Reg.RegNo == AMDGPU::VCC) {
2708 } else if (Op.isRegOrImmWithInputMods()) {
2709 Op.addRegOrImmWithInputModsOperands(Inst, 2);
2710 } else if (Op.isImm()) {
2712 OptionalIdx[Op.getImmTy()] = I;
2761 unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
2767 AMDGPUOperand &Operand = (AMDGPUOperand&)Op;
