Lines Matching refs:Op
612 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
615 switch (Op.getOpcode()) {
616 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
617 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
618 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
619 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
621 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
622 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
623 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
625 case ISD::FSIN: return LowerTrig(Op, DAG);
626 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
627 case ISD::STORE: return LowerSTORE(Op, DAG);
629 SDValue Result = LowerLOAD(Op, DAG);
636 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
637 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
638 case ISD::FrameIndex: return lowerFrameIndex(Op, DAG);
640 SDValue Chain = Op.getOperand(0);
642 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
645 SDLoc DL(Op);
648 Op.getOperand(2), // Export Value
649 Op.getOperand(3), // ArrayBase
650 Op.getOperand(4), // Type
656 return DAG.getNode(AMDGPUISD::EXPORT, DL, Op.getValueType(), Args);
662 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
667 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
668 EVT VT = Op.getValueType();
669 SDLoc DL(Op);
671 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
720 Op.getOperand(1),
725 Op.getOperand(2),
726 Op.getOperand(3),
727 Op.getOperand(4),
732 Op.getOperand(5),
733 Op.getOperand(6),
734 Op.getOperand(7),
735 Op.getOperand(8),
736 Op.getOperand(9),
737 Op.getOperand(10)
743 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
745 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
747 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
749 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
751 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
753 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
755 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
757 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
814 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
819 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
821 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
824 } // end switch(Op.getOpcode())
850 SDValue Op = SDValue(N, 1);
851 SDValue RES = LowerSDIVREM(Op, DAG);
857 SDValue Op = SDValue(N, 0);
858 LowerUDIVREM64(Op, DAG, Results);
882 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
885 SDLoc DL(Op);
886 SDValue Vector = Op.getOperand(0);
887 SDValue Index = Op.getOperand(1);
891 return Op;
894 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
898 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
900 SDLoc DL(Op);
901 SDValue Vector = Op.getOperand(0);
902 SDValue Value = Op.getOperand(1);
903 SDValue Index = Op.getOperand(2);
907 return Op;
910 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
916 SDValue Op,
919 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
921 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
931 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
934 EVT VT = Op.getValueType();
935 SDValue Arg = Op.getOperand(0);
936 SDLoc DL(Op);
945 switch (Op.getOpcode()) {
965 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
966 SDLoc DL(Op);
967 EVT VT = Op.getValueType();
969 SDValue Lo = Op.getOperand(0);
970 SDValue Hi = Op.getOperand(1);
971 SDValue Shift = Op.getOperand(2);
1001 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
1002 SDLoc DL(Op);
1003 EVT VT = Op.getValueType();
1005 SDValue Lo = Op.getOperand(0);
1006 SDValue Hi = Op.getOperand(1);
1007 SDValue Shift = Op.getOperand(2);
1011 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
1039 SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
1041 SDLoc DL(Op);
1042 EVT VT = Op.getValueType();
1044 SDValue Lo = Op.getOperand(0);
1045 SDValue Hi = Op.getOperand(1);
1057 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
1058 SDLoc DL(Op);
1063 Op, DAG.getConstantFP(0.0f, DL, MVT::f32),
1084 bool R600TargetLowering::isZero(SDValue Op) const {
1085 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
1087 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
1094 bool R600TargetLowering::isHWTrueValue(SDValue Op) const {
1095 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1098 return isAllOnesConstant(Op);
1101 bool R600TargetLowering::isHWFalseValue(SDValue Op) const {
1102 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1105 return isNullConstant(Op);
1108 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
1109 SDLoc DL(Op);
1110 EVT VT = Op.getValueType();
1112 SDValue LHS = Op.getOperand(0);
1113 SDValue RHS = Op.getOperand(1);
1114 SDValue True = Op.getOperand(2);
1115 SDValue False = Op.getOperand(3);
1116 SDValue CC = Op.getOperand(4);
1354 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1355 if (SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG))
1358 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1365 return SplitVectorStore(Op, DAG);
1368 SDLoc DL(Op);
1404 Op->getVTList(), Args, MemVT,
1509 SDValue R600TargetLowering::lowerPrivateExtLoad(SDValue Op,
1511 SDLoc DL(Op);
1512 LoadSDNode *Load = cast<LoadSDNode>(Op);
1523 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1527 Op.getOperand(2));
1565 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1566 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1573 return lowerPrivateExtLoad(Op, DAG);
1576 SDLoc DL(Op);
1577 EVT VT = Op.getValueType();
1690 Op.getOperand(2));
1698 Op.getOperand(2));
1709 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1710 SDValue Chain = Op.getOperand(0);
1711 SDValue Cond = Op.getOperand(1);
1712 SDValue Jump = Op.getOperand(2);
1714 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(),
1718 SDValue R600TargetLowering::lowerFrameIndex(SDValue Op,
1723 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
1729 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
1730 Op.getValueType());
