Lines Matching refs:Op
140 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
141 switch (Op) {
153 setOperationAction(Op, VT, Custom);
156 setOperationAction(Op, VT, Expand);
538 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
542 if (VT == MVT::i1 && Op == ISD::SETCC)
545 return TargetLowering::isTypeDesirableForOp(Op, VT);
1228 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1229 switch (Op.getOpcode()) {
1230 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
1231 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
1232 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
1234 SDValue Result = LowerLOAD(Op, DAG);
1243 return LowerTrig(Op, DAG);
1244 case ISD::SELECT: return LowerSELECT(Op, DAG);
1245 case ISD::FDIV: return LowerFDIV(Op, DAG);
1246 case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
1247 case ISD::STORE: return LowerSTORE(Op, DAG);
1251 return LowerGlobalAddress(MFI, Op, DAG);
1253 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1254 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
1255 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
1256 case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
1257 case ISD::TRAP: return lowerTRAP(Op, DAG);
1278 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
1280 SDLoc SL(Op);
1281 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
1472 SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
1474 SDLoc SL(Op);
1475 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Op);
1561 SDValue Op,
1563 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
1567 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
1571 EVT PtrVT = Op.getValueType();
1590 SDValue SITargetLowering::lowerTRAP(SDValue Op,
1595 Op.getDebugLoc(),
1603 return DAG.getNode(AMDGPUISD::ENDPGM, SDLoc(Op), MVT::Other,
1604 Op.getOperand(0));
1624 SDValue Op,
1627 SDLoc SL(Op);
1651 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1657 EVT VT = Op.getValueType();
1658 SDLoc DL(Op);
1659 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1689 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
1692 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
1697 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
1702 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
1708 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
1754 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1760 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1766 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1771 return lowerImplicitZextParam(DAG, Op, MVT::i8,
1799 Op.getOperand(1),
1800 Op.getOperand(2)
1808 Op->getVTList(), Ops, VT, MMO);
1812 Op.getOperand(1),
1813 Op.getOperand(2),
1814 Op.getOperand(3));
1817 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1821 Op.getOperand(1), Op.getOperand(2), Glue);
1824 if (Op.getOperand(1).isUndef() && Op.getOperand(2).isUndef())
1826 return Op;
1828 SDValue IJ = Op.getOperand(4);
1833 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1837 I, Op.getOperand(1), Op.getOperand(2), Glue);
1840 Op.getOperand(1), Op.getOperand(2), Glue);
1843 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
1845 return DAG.getNode(AMDGPUISD::INTERP_P1, DL, MVT::f32, Op.getOperand(1),
1846 Op.getOperand(2), Op.getOperand(3), Glue);
1849 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(5));
1851 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, Op.getOperand(1),
1852 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4),
1856 return DAG.getNode(AMDGPUISD::SIN_HW, DL, VT, Op.getOperand(1));
1859 return DAG.getNode(AMDGPUISD::COS_HW, DL, VT, Op.getOperand(1));
1873 Op.getOperand(1), Op.getOperand(2));
1876 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
1880 Op.getOperand(1), Op.getOperand(2));
1883 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
1884 Op.getOperand(4));
1888 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1892 Op.getOperand(1), Op.getOperand(2));
1895 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
1901 SDValue Numerator = Op.getOperand(1);
1902 SDValue Denominator = Op.getOperand(2);
1911 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
1915 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
1919 SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
1921 unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1925 MemSDNode *M = cast<MemSDNode>(Op);
1934 return DAG.getMemIntrinsicNode(Opc, SDLoc(Op), M->getVTList(), Ops,
1942 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1945 SDLoc DL(Op);
1946 SDValue Chain = Op.getOperand(0);
1947 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1951 Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3));
1954 Op.getOperand(2), Glue);
1959 Op.getOperand(2),
1960 Op.getOperand(3),
1961 Op.getOperand(4),
1962 Op.getOperand(5),
1963 Op.getOperand(6),
1964 Op.getOperand(7),
1965 Op.getOperand(8),
1966 Op.getOperand(9),
1967 Op.getOperand(10),
1968 Op.getOperand(11),
1969 Op.getOperand(12),
1970 Op.getOperand(13),
1971 Op.getOperand(14)
1974 EVT VT = Op.getOperand(3).getValueType();
1981 Op->getVTList(), Ops, VT, MMO);
1984 if (const ConstantFPSDNode *K = dyn_cast<ConstantFPSDNode>(Op.getOperand(2))) {
1989 return Op;
1996 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1997 SDLoc DL(Op);
1998 LoadSDNode *Load = cast<LoadSDNode>(Op);
2025 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
2049 return SplitVectorLoad(Op, DAG);
2061 return SplitVectorLoad(Op, DAG);
2066 return SplitVectorLoad(Op, DAG);
2074 return SplitVectorLoad(Op, DAG);
2080 return SplitVectorLoad(Op, DAG);
2087 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2088 if (Op.getValueType() != MVT::i64)
2091 SDLoc DL(Op);
2092 SDValue Cond = Op.getOperand(0);
2097 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
2098 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
2116 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
2117 SDLoc SL(Op);
2118 SDValue LHS = Op.getOperand(0);
2119 SDValue RHS = Op.getOperand(1);
2120 EVT VT = Op.getValueType();
2143 const SDNodeFlags *Flags = Op->getFlags();
2157 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
2158 if (SDValue FastLowered = LowerFastFDIV(Op, DAG))
2161 SDLoc SL(Op);
2162 SDValue LHS = Op.getOperand(0);
2163 SDValue RHS = Op.getOperand(1);
2225 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
2227 return LowerFastFDIV(Op, DAG);
2229 SDLoc SL(Op);
2230 SDValue X = Op.getOperand(0);
2231 SDValue Y = Op.getOperand(1);
2292 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
2293 EVT VT = Op.getValueType();
2296 return LowerFDIV32(Op, DAG);
2299 return LowerFDIV64(Op, DAG);
2304 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2305 SDLoc DL(Op);
2306 StoreSDNode *Store = cast<StoreSDNode>(Op);
2329 return SplitVectorStore(Op, DAG);
2337 return SplitVectorStore(Op, DAG);
2341 return SplitVectorStore(Op, DAG);
2349 return SplitVectorStore(Op, DAG);
2352 return Op;
2355 return SplitVectorStore(Op, DAG);
2362 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
2363 SDLoc DL(Op);
2364 EVT VT = Op.getValueType();
2365 SDValue Arg = Op.getOperand(0);
2372 switch (Op.getOpcode()) {
2374 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
2376 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
2382 SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
2383 AtomicSDNode *AtomicNode = cast<AtomicSDNode>(Op);
2389 return Op;
2393 SDLoc DL(Op);
2394 SDValue ChainIn = Op.getOperand(0);
2395 SDValue Addr = Op.getOperand(1);
2396 SDValue Old = Op.getOperand(2);
2397 SDValue New = Op.getOperand(3);
2398 EVT VT = Op.getValueType();
2405 return DAG.getMemIntrinsicNode(AMDGPUISD::ATOMIC_CMP_SWAP, DL, Op->getVTList(),
2733 static bool isKnownNeverSNan(SelectionDAG &DAG, SDValue Op) {
2737 return DAG.isKnownNeverNaN(Op);
2774 // Only do this if the inner op has one use since this will just increases
3064 /// \brief Analyze the possible immediate value Op
3173 SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32);
3174 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
3185 static bool isFrameIndexOp(SDValue Op) {
3186 if (Op.getOpcode() == ISD::AssertZext)
3187 Op = Op.getOperand(0);
3189 return isa<FrameIndexSDNode>(Op);
